Electronic – How to implement a tri-state buffer for a vector in VHDL

buffertri-statevhdl

I want to implement a tri-state buffer for a input vector, triggered by an enable vector, where every bit of the enable vector enables the corresponding bit of the input vector.

Something like this but with multiple enable bits:

A 4 bit tri-state buffer but with a single enable bit.

A single tri-state buffer looks like this:

Y <= A when (EN = '0') else 'Z';

(example from: https://startingelectronics.org/software/VHDL-CPLD-course/tut16-tri-state-buffer/ )

It could look like this (but that one doesn't work…):

[...]
signal Y : std_logic_vector(N downto 0);
signal A : std_logic_vector(N downto 0);
signal EN : std_logic_vector(N downto 0);

Y <= A when EN = (others => '1') else (others => 'Z');

Is there a way to declare this in VHDL or do I have to write a buffer for every bit?

Edit:
To clarify I'm searching a short declaration for this:

Y(0) <= A(0) when EN(0) = '1' else 'Z';
Y(1) <= A(1) when EN(1) = '1' else 'Z';
[...]
Y(N) <= A(N) when EN(N) = '1' else 'Z';

Best Answer

If you need enable control for each bit, then the easiest way is to use a generate statement:

tristate : for i in 0 to N generate
begin
    Y(i) <= A(i) when EN(i) = '1' else 'Z';
end generate tristate;

Generate statements with for constraints create multiple circuits which operate in parallel, unlike a for loop in programming where the same code is executed multiple times in series.

Related Solutions

Electronic – Why does VHDL function declaration not accept bounds for the return type, e.g. std_logic_vector

This is mostly for Jonathan Drolet but there's also a lesson here. Note that parameter argument to my_function supplies a type mark with a subtype indication. This is valid in VHDL.

library ieee;
use ieee.std_logic_1164.all;

entity myfunc is
end entity;

architecture foo of myfunc is
    function my_function(lv: std_logic_vector(3 downto 0)) 
            return std_logic_vector is  
    begin 
    return lv & "000";
    end function;

    constant fumble:  std_logic_vector (3 downto 0) := x"E";
    signal humble:    std_logic_vector (6 downto 0);
begin
    humble <= my_function(fumble);

end architecture;

This code analyzes, elaborates and simulates.

Note that the return mark is an unconstrained subtype and the result value is assigned to a declared signal with a subtype indication (supplying an index constraint).

There are rules specifically for determining the effective value of a signal that require the bounds be checked after an implicit subtype conversion. Providing a return value that doesn't match the bounds of humble would result in a run time error causing simulation to end without successfully completing.

In other words a constraint isn't necessary here. The return value subtype indication is derived internally, and as is shown in this from the input parameter.

Electronic – Testbench for INOUT port in VHDL

You're trying to create a tri-state signal on 'data' of unresolved type std_ulogic_vector. The 'unresolved' means that it doesn't use a resolution function when establishing the value of a signal (i.e. a 'signal' or 'port').

A resolution function takes the value from each of the sources onto a signal and resolves them all into a single assignment value.

So the unresolved datatype you have selected only allows one source, by definition. The solution is to use a resolved type because they deal with multiple sources onto a single signal, which is what you wanted to implement.

The typical resolved types here are std_logic and std_logic_vector instead. (You don't explain why you don't want to use them, only that you don't.)

Incidentally, the initial values on your signals don't constitute another source. They're just values your simulator will start off with in the signals. In their absence, your simulator would put 'U's on the signals you have.

Best Answer

Related Solutions

Electronic – Why does VHDL function declaration not accept bounds for the return type, e.g. std_logic_vector

Electronic – Testbench for INOUT port in VHDL

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