Electronic – How to learn HDL

1. Is there any documentation for that is generic or covers Spartan-6 LX9 board?

   The DCM is fully contained within the FPGA chip. So it doesn't matter what board you have. The documentation will be based on what chip you have.

   For the Spartan-6 family, see the Spartan 6 Clocking Resources User Guide

2. Is using this module is absolutely necessary in this example? Is that possible to do the same thing easily w/o using that module?

   If you're just blinking LEDs, you probably don't need to use the DCM. Probably they used it because its a very complicated block and they specifically wanted to provide an example of using the DCM without much else in the way of complex logic to confuse things.

3. How people usually go about vendor specific things like clock? For example, if one wants to target both Altera FPGAs and Xilinx ones. What is the process to achieve that? Is it similar to ordinary C pre-processor typedefs etc?

   Unfortunately, complex hard cores like clock management is one of the areas where there's not much compatibility between vendors. You'll likely have to make significant code changes if you want a design using these features that is portable between two device families, whether they're from the same or different vendors.

   If you can simplify your interface so that you just have one input clock coming from off-chip, and a number of derived clocks that are distributed to the rest of your logic, the cleanest solution is probably to push all of the vendor-specific code into a single module that you can instantiate in your top-level code. Then you can just use a different "clock management" module depending which device you're targeting.

   If you want to do something like dynamically changing the phase relationship between various clocks, or switch between several choices of reference clock frequency, you probably have no choice but to re-code substantial chunks of logic for different target devices.

   Remember that in addition to the Verilog code, there will probably also be numerous constraints that need to be defined, and these will also need to be different for different devices.

It has to do with what can be easily evaluated at elaboration time, formally, what is called a "locally static expression". This is an obscure looking rule, but it deserves some thought - eventually it does make some sense, and your simulator is quite correct in alerting you by generating non-obvious results.

Now, temp(1) can be evaluated at compile time (even earlier than elaboration time) and it can generate a driver on bit 1 of "temp".

However, temp(i) involves a bit more work for the tools. Given the trivial nature of the loop bounds here ( 1 to 4 ) it is obvious to us humans that temp(0) cannot be driven and what you are doing is safe. But imagine the bounds were functions lower(foo) to upper(bar) in a package declared somewhere else... now the most you can say with certainty is that temp is driven - so the "locally static" expression is temp.

And that means that the process is constrained by these rules to drive all of temp, at which point you have multiple drivers on temp(0) - the process driving (no initial value, i.e. 'u') and the external temp(0) <= '0';. So naturally the two drivers resolve to 'U'.

The alternative would be a "hacky little rule" (opinion) that if the loop bounds were constants, do one thing, but if they were declared as something else, do something else, and so on ... the more such oddball little rules there are, the more complex the language becomes... in my opinion, not a better solution.