I have a Max10 dev board with a 10m08 chip on it. I made a simple counter to blink the LED's. My counters have asynchronous resets, and my asynchronous reset has a circuit to keep it low for two clock cycles and prevent metastablity. I reset the fpga and it the counters stop (they all go to zero), it only starts counting when I upload a new flash to the dev board. If I power down the FPGA and power it back up I get the same result. This leads me to believe that its not my reset and its more of a flashing problem. Is there some kind of setting to make the flash stick? or should I go back to debugging. How do you make the flash persistent, I don't see an option for that in the programmer, do you have to configure the user flash?
Electronic – How to make an .sof upload to an Altera Max10 stick
fpgaintel-fpga
Related Topic
- Electronic – Best utillization of M9K memory in max10 or other altera fpga’s
- Electronic – Configure (upload bitstream) to MAX10 without Altera tools using Linux
- Electrical – Altera MAX10 CPLD initialization IO state
- Electronic – Fairly Simple VHDL SPI bus working in simulation but not on FPGA (Lattice MACHOX3LF-6900C FPGA and Lattice Diamond software)
- Electronic – Altera Max10 3.3V interface
- Electronic – Altera MAX10 Clock primitives without synchronization
- Electrical – Altera Max10 altPLL slack
Best Answer
I answered a question here that details some of the different types of FPGA file formats: FPGA: Bitstream vs. SRAM Object File
Basically, right now, you're flashing just the SRAM with the SOF (SRAM Object File) -- this is volatile, and will be lost at power down or reset. SRAM FPGAs generally load their configuration from a configuration memory on-board, or a microprocessor that configures it (via ISP or similar).
In your case, your MAX10 dev board has a built-in USB Blaster device that should be able to program the on-board configuration memory. See page 4-4 of the user-guide and how to generate and program a POF instead of a SOF. This will keep your configuration on the flash memory device, and it will get loaded at every power-on.
I believe the Quartus II programmer can download a small executive to the FPGA (via JTAG) that then provides access to the SPI memory. It then uses that temporary executive to flash the SPI memory, and then resets.