# Electronic – How to minimize characteristic impedance mismatches caused by vias

characteristic-impedancepcb-designRFvia

This question springs from an answer here.

When using stripline configurations for rf signalling, the conductors are routed on an inner layer of the pcb, sandwiched between two ground planes.

I understand that vias cause mismatches in the characteristic impedance, which I would like minimize. My frequencies are 2.4 GHz and 3.5 GHz.

Which aspects should I consider when carrying rf signals through vias? For example:

1. Drill size
2. Annular ring thickness
3. Distance from rf source
4. etc?