As I understand it, pipelining is used to speed up the clock frequency by processing more instructions at once, and longer pipelines should improve the clock frequency. However, my instructor mentioned that in some cases pipelining could actually hurt the clock, particularly when splitting on the memory stage. I'm having trouble envisioning how this is possible– surely it could hurt the CPI due to hazards, but it seems like the clock frequency should be unaffected. Can somebody point out to me what I'm missing?
Electronic – How to pipelining hurt the clock frequency
clock
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Best Answer
I think that your question is aimed at the program execution speed, and not the clock frequency.
This link has a simple way to explain pipeline. But the picture below (from the site) brings the base information on how the pipeline structure can hurt the execution speed:
From the picture you can see that the pipeline takes advantage of executing two or more tasks simultaneously. The problem is that the period of execution for one cycle is dependent of the longest task in the pipeline. If lots of long tasks enters in the pipeline, the whole chain may suffer the delay. Among these kind of tasks, memory instructions are one of the longest.
If all the memory access are made scattered through the code, the processing time would be higher. If the accesses are grouped, the fast instructions would be executed without the interference of the slower ones.
Other problem that may arise is the junction of pipeline and branch prediction. The prediction tries to guess which is the more probable result from an
ifinstruction and starts to evaluate the guessed path from code even before the result is known. All these instructions are therefore pipelined through the processor. If the guess appears to be wrong, the processor must wait until the pipeline buffer to clear before starting to evaluate the correct path.