Let's assume that the latches in the 16-bit counter and the 8-bit latch are edge-triggered D latches. Thus, when
clk goes from 0 to 1 the counter will naturally 'increment' (e.g.
0008hex) and the 8-bit latch will 'save' its contents.
Note how the first bit of the counter is just inverted
clk. Thus, the 'adder with memory' circuit proposed wouldn't work, right? Because we'd only be adding every other number in memory?