Electronic – How to remove this warning in Verilog

system-verilogverilogxilinx system generator

I took a signal sum[8:0] in my code. Further, I need only sum[8] in my code (M.S.B of sum). So I used the statement assign sum[7:0]=0;

It gave me the following WARNING after synthesis:

WARNING:Xst:646 – Signal < sum<7:0>> is assigned but never used. This
unconnected signal will be trimmed during the optimization process.

Should I worry about it or ignore it?

Best Answer

If you know that you don't need the signals, ignore the warning. But why would you declare a 9 bit bus whilst only needing one signal? That's bad practice.

Generally about such warning:

You should definitely worry about it!

This warning means that you're not using signals that you've declared so synthesis -- being the clever thing that it is -- optimised those away. This usually suggests that there's something logically wrong in your implementation and that your output will not be what you intend it to be.

Only ignore warnings that you fully understand.

Finally, don't switch off that warning type as you will not see it when it actually matters!

Related Solutions

Connected to Multiple Drivers Problem Verilog

Here, the signal BCD0 is being assigned values under 3 separate 'always' processes. Hence the synthesis is returning multiple driver error. Try moving all assignments of BCD0 signal under a single 'always' process. That will solve the issue. You could use different conditions under the same always block itself to define the behaviour of the signal.

The BCD counter which you are trying to implement is sensitive to clock edges, clear, up as well as down signals. So the process should be sensitive to clock edges and all other signals can be sensed w.r.t clock edges. One way of rewriting the code is like:

always @(posedge Clock) begin  
  if (Clear) begin  
    BCD1 <= 0;  
    BCD0 <= 0;  
  else if (up == 1) begin  
    if (BCD0 == 4'b1001) begin  
        BCD0 <= 0;  
        if (BCD1 == 4'b1001)  
          BCD1 <= 0;  
        else  
          BCD1 <= BCD1 + 1;  
        end  
    else  
        BCD0 <= BCD0 + 1;  
    end  
  else if (down == 1) begin  
    if (BCD0 == 4'b0000) begin  
        BCD0 <= 4'b1001;  
        if (BCD1 == 4'b1001)  
          BCD1 <= 4'b1001;  
        else  
          BCD1 <= BCD1 - 1;  
        end  
    else  
        BCD0 <= BCD0 - 1;  
    end  
  end  
end

Here, all sensitivity conditions of both BCD0 and BCD1 signal are captured under a single 'always' block which will synthesize it properly.

Electronic – Synthesis of a multiplier design

I presume that you are synthesising for an FPGA or CPLD. The simulator will successfully simulate many language constructs which are technically valid Verilog, but are very hard to translate to real programmable logic hardware.

I can't synthesise your block myself as I don't have the part_prod_gen1, count_one and shift modules available, but the problems I can see from reading the code are:

Using posedge and negedge always@ blocks for signals other than clock and reset lines often isn't synthesisable (see this answer). I think that using shift registers (explicitly or with a signal_old register) is a much more reliable approach than testing for posedge of count[0].

Register array qq elements are assigned in multiple separate processed (always blocks). This is not synthesisable as the process blocks run in parallel and the register flip-flop cannot be set from two different sources. You can rectify this by combining much of the code into a single sequential process (which is ugly and harder to debug) or using intermediate wires which are combined together in a single process. See this answer for a similar problem.

genvar j, i,  k, m;
// ... other code
//load the partial products
generate
  for (j=1; j<=16; j=j+1)
  begin: loop1
    always @ (posedge clk)
    begin
      if (!reset) begin
      // ... qq assignments
      end
    end
  end
endgenerate

/* should be */

genvar i,  k, m;
integer j; // j as integer not genvar
// ... other code
//load the partial products
//generate // comment out or remove
always @ (posedge clk)
begin
  for (j=1; j<=16; j=j+1) // <- for-loop inside always block
  begin: loop1
    if (!reset) begin
    // ... qq assignments
    end
  end
end
//endgenerate // comment out or remove

Best Answer

Related Solutions

Connected to Multiple Drivers Problem Verilog

Electronic – Synthesis of a multiplier design

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