Electronic – How to route many FPGAs in JTAG chain

Purely answering how to create a parametrised width zero. hopefully another answer can cover the best practise for multiple drivers.

localparam DATA_W = 8;
i = {8{'1b0}} ;

or

i = 'b0 ; //RHS width is matched to LHS, early version limited to 32bits

or

i = '0;  //Introduced in 2012 SystemVerilog simplest way to x every bit : 'x

The typical thing to do on Cortex parts that only have a single processor core is to only use SWD. In this case, the only lines which need to be routed to the 10-pin header are SWDCLK/SWDIO/SWO/!RESET/+3V3/GND. Notice that !RESET is the microcontroller reset, and is not the same as TRST. From my experience, the only pin that needs to be pulled up via a resistor is !RESET, at least using a Ulink2/Ulink ME debug adapter. On most Cortex processors, the JTAG and SWD lines are actually shared, for example, SWO is the same pin as TDO, but that appears to not be the case here. If your tools support both JTAG and SWD, you can pick the system which conflicts the least with your other peripheral/pinning needs. If you must share the debug pins with other hardware, then the ISP pin should be pulled up and wired to one of the GND pins on the 10 pin connector (the GND pins are internally shorted on the debug adapter so that it will pull down when the debugger is connected, allowing you to enter ISP mode).

In general, SWD requires fewer pins, and can use SWV (Serial Wire Viewer) which gives you printf redirection and other features, while JTAG allows for chaining (and access to both cores on dual core parts such as the LPC4300), and is the only option for older tools.

The part number for the shrouded connector is FTSH-105-01-F-D-K, but in practice it is difficult to find, but you can probably put out a RFQ on Alibaba or a similar B2B site.