analogdigital-logicgate-drivingmosfetswitches
I have an NMOS that is switching too fast for my application. Into the gate I am sending a logic-level square wave (PWM). Unfortunately for me, as expected, the output is also a near square wave.
How can I get the Vout to be more trapezoidal? Or said another way, what is the simplest modification I can make to decrease the slew rate at the output?
Note: (Vin) is the voltage applied at the gate of the NMOS & (Vout) is the voltage seen at the drain of the NMOS.
I think you may be exceeding what is known as the volt-microsecond limit for the transformer. Basically this figure tells you how long you can apply a pulse of a certain voltage before the voltage reverses. Real transformers will saturate and the V.\$\mu s\$ limit tells you, in practical terms how far you can push the transformer.
The waveform initially looks good on the rising edge - it attains a peak of 4 or 5 volts (it looks that way from your pictures) but after about 10 us it goes wrong - this means your transformer is probably rated as having a volt-microsecond product of about 50.
Other problems with the circuit are: -
Here is a helpful (in parts) article on the subject. And here is a helpful guide on designing transformer circuits for driving mosfets: -
You can probably see in one of the diagrams (fig 3) the problem you are getting.
The reason the FET turns off so slowly is because you only have 2 kΩ pulling it high. Take a look at the datasheet for that FET. It should show you the actual and effective gate capacitance when switching. The relatively weak 2 kΩ pullup is working against that capacitance.
Here is a trick I sometimes use in this situation:
The double emitter follower is basically a impedance buffer. The current to charge and discharge the gate capacitance is handled by Q1 and Q2, so the signal at GATE can be much higher impedance and still switch the FET quickly. Note that this double emitter follower will loose 700 mV or so on each end. That is fine for a FET that switches over a 10 V gate range. It will still be "off" with 700 mV on the gate just as well as with 0. At the other end, its usually easy enough to drive GATE the extra 700 mV further than what you want to make sure shows up on the gate of Q3.
Best Answer
The only control you have over the resistance of the FET is the gate-source voltage. You need to slow down the change of that voltage. The most common way of doing that is an RC filter at the gate. Put a resistor between your drive source and the device gate, and the gate's parasitic capacitance will form an RC filter. The bigger the resistor, the slower the turn-on and turn-off.
If the resistor gets too big, you can have noise immunity issues (false gate triggers and such), so past a certain resistor value (maybe in the 10k-100k range) you're better off adding capacitance gate-source to slow the switching down further.
As a general rule, I always put an RC filter with a pulldown resistor on all FETs. This allows control of the rise-time, and provides improved noise immunity.
simulate this circuit – Schematic created using CircuitLab
Keep in mind that any time your FET spends not fully "on" or "off", it sees increased losses. If it's on, the device has very low voltage across it. If it's off, the device has no current through it. Either way, low loss. But if you're in between, the device sees both voltage and current, meaning its power dissipation is far greater during that period. The slower you switch, the greater that loss becomes. At what point it becomes a problem depends on the FET, the source, and the switching frequency.