In general, datasheets give excellent advice that you ignore at your own peril.
(Alas, like the advice of Cassandra, the advice in datasheets is often correct but misunderstood until it is too late).
However, even the writers of datasheets occasionally make mistakes.
The Burr-Brown application bulletin "Analog-to-Digital Converter Grounding Practices Affect System Performance" reports one experiment where a PCB was layed out both ways, and shows "a single ground plane" works best, even when it contradicts the "split grounds" advice given in a datasheet.
Splitting ground planes often seems to make an improvement.
Making a single ground plane and fixing the actual source of the problem is even better.
The Henry Ott article you linked and other "unsplit ground" articles at the MassMind explain why.
In mixed signal PCB the analog and digital ground has to be separated
like the following image:
That diagram looks like Figure 3 of the
"partitioning and layout of a mixed signal pcb" article by Henry W. Ott in "printed circuit design" magazine (June 2001).
On the same page as that diagram, Ott says "Why do we need to split the ground plane ... ? The answer is we don't! Therefore, I prefer the approach of using only one ground plane and partitioning the PCB into digital and analog sections."
Later in the article Ott says "in almost all cases, both the functional performance and the EMC performance of the board will be better with the single ground plane [than with] split ground planes".
Use one solid unsplit ground plane under both the analog and the digital parts of the board.
Which layer and how should I route the analog sources(1V8,3V3) and
grounds for the MCU ADC?
While many BGA parts only require 4 layers, it appears at first glance that this particular BGA package requires a minimum of 6 layers.
One common layer stackup for 6 layer boards is
1 signal
2 signal
3 power
4 ground
5 signal
6 signal
As shown the the documentation you already linked to:
The ground plane is one solid unsplit ground plane -- with holes around vias just passing through, sold connections to GND vias, and thermal relief around GND through-holes.
The power plane is chopped up into the various power supplies required for different regions of the board, with similar holes.
(Sometimes it's better to route less-common power voltages on the signal layers of the board, rather than cut it out of the power plane).
on the ... bottom ... layer. Can I place there the crystal oscillator as well?
The vast majority of systems I've seen have all the components of a Pierce oscillator (the inverter, the crystal, two capacitors, and sometimes a series resistor) all on the same side of a PCB.
However, I have seen a system where the crystal was on the opposite side (Hamish Kellock OH2GAQ)
and a paper that seems to recommend putting the two capacitors on the opposite side
(Texas Instruments "PCB Design Guidelines For Reduced EMI").
So I'm pretty sure the oscillator will oscillate with the crystal on the opposite side from the inverter.
As always, the EMI emitted (and the susceptibility of the oscillator to outside noise) is proportional to the loop area.
Most of the time, it gets bigger (worse) if you put the crystal on the opposite side.
(I don't know if your particular BGA package is one of the exceptions).
Best Answer
Sorry, my bad. I posted this image from the CY8C32 datasheet into my answer to the other question:
but didn't copy the caption. "Figure 2-8. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance". This is for the TQFP100 part, which doesn't have the thermal pad, and doesn't apply to the QFN48 you're using.
For parts with a thermal pad the split makes no sense, and you should connect the thermal pad to digital ground.
Note that when you use a thermal pad on your PCB that you shouldn't apply solder paste all over it, but use a windowed stencil to avoid the IC being pushed up by the solder paste:
Further reading
CY8C32 datasheet
HVQFN application information, NXP application note