Electronic – How to wire a system for Nios 2 in Qsys

Your code is okay, I managed to compile it with ghdl. But only after I replaced the backticks. Here's how it looks in hex:

$ hd -s 0x2ee -n 7 test.vhd.orig 
000002ee  e2 80 99 5a e2 80 99                              |...Z...|

The compiler won't accept that as '. You said you've replaced them in the comments, but obviously something went wrong. Just delete the whole line and type it by hand. You learn a lot more anyway, if you don't just copy and paste..

I tried all ways to write ' and that might not even be the problem since it appears that the compiler is complaining about the row where it says begin

The line number the compiler tells you, isn't always where you've made a mistake. Just take it as a hint. For example if you forget a ; the compiler usually indicates the error where the next statement begins.

A good debugging strategy for obscure errors is to remove lines until your code compiles. That helps to find the exact location and works especially well with VHDL (compared to other programming languages).

At least the following need fixing:

• Break the link between clk_0\clk_in_reset and jtag_uart_0\reset - you have made a bad connection (at random?) here in an attempt to fix warnings.
• In System Contents on the nios2 block
  • Leave custom_instruction_master should be disconnected
  • Jtag MM slave jtag_debug_module should be disconnected for now - you will sill have external debugging via. the FPGA JTAG lines without connecting this.
• Signal clk_in_reset in the clk0 Clock Source needs to be exported. Nothing is driving your entire system reset line at the moment, so nothing will work. Later you can tie the exported signal appropriately to a board level reset. To do this: double click in the export column and type "reset_in" or similar.
• The LED driver component leds has a port called conduit_end. This will be the wires you will connect to pins on the chip to drive the LEDs. To get this signal out of QSYS you also need to 'export' it as before - double click in the export column, type a name like "led_pins" and then this warning will be gone: Warning: System.leds: leds.conduit_end must be exported, or connected to a matching conduit.

• You added an Avalon MM-slave port on the leds component without fully-specifying the interface details. At least you need to say which other ports of leds control the clock and reset for those memory accesses. This is how you fix this warning: Error: System.leds.avalon_slave_0: leds.avalon_slave_0 must declare an associated reset

  • Open up the component editor for leds by right clicking it in the library (NOT the design), then choose Edit....
  • Go to the Interfaces tab
  • Find the section called avalon_slave0 (Avalon Memory Mapped Slave) and choose values for the Associated Clock and Associated Reset dropdown boxes.
  • Click Finish from the Component Editor.
  • Return to QSYS and hit File -> Refresh System

• You also need to edit the leds component and on the Interfaces tab, click Remove Interfaces with No Signals button in order to delete the empty interfaces (reported as System.leds.reset: Interface has no signals). These are often auto-created by QSYS when it badly auto-detects your interface setup (inferred from port names). You need to remember to clean them up. Save the component and then reload QSYS to see this one go away.

General point of order: try not to exit the component manager while it has warnings. You should fix those before moving on to integration.

• Your sram should definitely have a clock and reset signal added on the internal side to go with the Avalon-MM interface, and the interface needs configuring to use them as with leds.
• If the sram block is supposed to drive an external memory chip through the conduit port, rather than use internal block rams, you will have a great deal of fun getting that to work.
  • Consider replacing sram module with stock parts for now - look under Library -> Memories and Memory Controllers -> On-Chip -> On-Chip Memory (RAM or ROM). That will use block rams to implement your Nios RAM without having to use external memory - sufficient to see the CPU boot over JTAG.
• connect jtag_uat_0\reset to clk0\clk_reset, so that the JTAG uart peripheral is reset with the rest of your system.

It is not difficult to build this stuff in QSYS once you get the hang of it - if you haven't already then work through the Altera video tutorials at altera.com to get to grips with the tool.

The reason why you need to link up the clock/reset for every Avalon-MM port (and declare as such to QSYS) is so that it can check the clock domains and insert clock crossing logic for you when required. QSYS can cross domains, burst settings, memory widths and base addresses - it's great for this stuff.