Im working on a display project and have run into some I2C issues. The display is of 3.3V design, so I figured, no big deal, ill use a level shifter and be on my merry way. Well, sure enough the level shifter kind of worked, at least it looked good, until i put the scope on it. I am was running with a low voltage of about 1.6V during the slaves ACK. The devices worked, but this is not in spec and I can't rely on this working across multiple devices. So, I'm wondering if anyone knows of a way to sink the extra current during the ACK while not effecting the input waveform from the master.
The display can only sink 1mA, but for the level shifter to work appropriately I need to sink the current from the high side pull ups as well as the low side, so about 2.5mA in the current setup.
I have tried using a pnp transitor with the slave device connected to the base and the low side of the level shifter connected to the emtiter with the collector across a current limiting resistor to ground. I then tied the emitter to the slave with a resistor. This worked to pull the ACK to about .1V, but the series resistor in line from the emitter to the display distorts the waveform from the master too much to be comfortable.
So, if anyone has any other ideas I would be greatful. Perhaps there is a purpose made solution that I can't google my way into.
Best Answer
Level shifters for I2C devices are easy to make if you know the correct technique. Remember that the I2C physical interface layer uses open drain type drivers designed to pull to GND. A pullup resistor is used to place the signal line into the high level when the driver stops pulling down.
Your question did not give enough information to be able to know what voltage you need on the opposite side of the translator from the display. For purposes of an example I'll show the circuit to use for translating from a 5V I2C swing to a 3.3V I2C at your display. You will need to make two of these circuits, one for the SDA line and one for the SCL line.
The BSS138 is an N-channel MOSFET. In this circuit configuration the drain (D) goes to the interface side with the higher voltage. Likewise the source (S) goes to the lower voltage side. We tie the gate (G) to the lower of the two interface voltage levels. A resistor is added to help protect the gate from transients on the voltage rail. The 0.1uF capacitor is very important so that the gate of the MOSFET does not get disturbed by capacitive coupling of transitions on the drain or source.
Note that the body diode of the MOSFET plays an important role in the operation of this circuit. If you try to use this circuit with voltage levels less than 3.3V it may be necessary to utilize a N-FET with a lower VGSth than the 1.5V threshold offered by the BSS138.