Electronic – Icarus verilog syntax error in a generate block

development-toolsverilog

In the top level of a module, I have the following block:

   genvar i;
   generate 
      for (i = 0; i < DEPTH; i++) begin
       fifo_element #(WIDTH) element (.clk(clk), 
                       .d_in(e_qd[i]), 
                       .d_in_strobe(e_in_strobe[i]), 
                       .q(e_qd[i+1]),
                       .q_ready(e_qready[i]), 
                       .in_strobe_chain(e_in_strobe[i+1]), 
                       .q_out_strobe(e_out_strobe[i+1]), 
                       .out_strobe_chain(e_out_strobe[i]),
                       .prev_used(i == 0 ? 1'b0 : e_used [i-1]), 
                       .next_used(i == DEPTH-1 ? 1'b1 : e_used [i+1]), 
                       .used(e_used[i]));
    end // for (i = 0; i < DEPTH; i++)
   endgenerate

When I attempt to compile this with icarus verilog (v10.1, using the -g2009 command line option) I get the following errors:

fifo.v:84: syntax error
fifo.v:96: error: invalid module item.
fifo.v:97: syntax error

These errors correspond to the line containing for, the last line of the element instantiation, and the line containing the end that corresponds to the begin of the for block. If I delete the apparently-unnecessary begin and end markers the third error goes away but the other two remain.

What's wrong with my code? Or is this a problem with Icarus Verilog? (A little research suggests that while earlier versions didn't support generate blocks at all, they've been supported for some time now, so what I'm trying to do here should work)

Best Answer

Maybe you need i = i +1 instead of i++. Other than that, I don't see anything obviously wrong.

Related Solutions

Electronic – “is not declared” error in Verilog

You need to give the instance a name (see below)

It also looks like you may be trying to declare it in an always block, this won't work. Declare it outside any blocks (e.g. at the top of the module)

Also, using the "connection by name" (or named association) method of instantiation rather than "connection by order" (or positional association) is less prone to accidental errors from getting the order wrong, especially with modules with many ports.

So the instantiation for connection by name would be

encoder8to3 enc_instance (.A(LL), .B(x), .F(FAULT));

With this method it could be written like this and still be correctly connected:

encoder8to3 enc_instance (.A(LL), .F(FAULT), .B(x));

Whereas using:

encoder8to3 enc_instance (LL, FAULT, x);

would connect B to FAULT and F to x.

Here's a reasonable pdf on modules and instantiating them. I agree good Verilog tutorials are quite thin on the ground (compared to something like C) so starting out can be a bit bewildering.
If you can find a copy at a reasonable price, I do highly recommend the Pong Chu book "FPGA Prototyping with Verilog Examples" I mentioned in my answer to your other question, as well as the focus on synthesis I mentioned, it goes through everything you need to start writing decent code, and is very clear and concise.
There is also a google mailing list for Verilog you might find of use, and fpga4fun has some good tutorials and a forum. And of course there is here :-)

EDIT - about where to declare the module:

The instantiation only connects the ports together, so where you declare it (outside a block) doesn't matter.
If you want to do something with this module inside the always block use some intermediate logic. Create a couple of registers, use the always block to manipulate them as desired, then tie these to the instantiated module ports (in the instantiation).

The way you have it at the moment, the instantiated module can be seen as in parallel with your module rather than inside it, as it just connects directly to the inputs and output of the module. Have a look at the RTL schematic to see what is being generated by the code (under synthesis in the design tab)

Electronic – Verilog – Referencing Flattened Busses in Module Instantiation

It seems like you are running into Verilog's Escape identifiers gotcha:

§2.7.1 Escaped identifiers

Escaped identifiers shall start with the backslash character () and end with white space (space, tab, newline). They provide a means of including any of the printable ASCII characters in an identifier (the decimal values 33 through 126, or 21 through 7E in hexadecimal).

Neither the leading backslash character nor the terminating white space is considered to be part of the identifier. Therefore, an escaped identifier \cpu3 is treated the same as a nonescaped identifier cpu3.

So not only you need to properly write down escaped port name, but you also need to make sure you don't forget to put a whitespace at the end. For example:

DES_SBOX1 feistel( .CLK(CLK_tb),
                 .\ptext[5] (ptext_tb[5]),
                 .\ptext[4] (ptext_tb[4]),
  ...

Hope it helps. Good Luck!

Best Answer

Related Solutions

Electronic – “is not declared” error in Verilog

Electronic – Verilog – Referencing Flattened Busses in Module Instantiation

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