Electronic – Identifying an old RF circuit

In some cases it is possible to replace DRAM with SRAM, by adding some logic to latch the row address. Whether this will work in a particular circuit depends on the timing of the RAS, CAS, and /WR signals and how the SRAM responds to them. 1 bit DRAMs have separate data input and output pins. If these are not tied together in the circuit then you may also need a Tri-State buffer to bridge between them. Getting the timing right could be tricky.

Here are two examples that work:-

SRAM replacement for lower 16K ← ZX Spectrum

SRAM replacement for TMS99x8 VRAM

You may be able to use higher capacity DRAMs provided that they are compatible - compare their data datasheets to make sure. The main things to watch out for are RAS/CAS timing (Fast Page Mode, EDO etc.) and refresh requirements.

However replacing the the faulty DRAMs with correct equivalents would be much easier and more likely to succeed. Although these older DRAMs are no longer manufactured, many are still available on the second hand market - usually selling at much cheaper prices than when new.

You may not have found what you want because you haven't searched all the equivalent part numbers. eg. '41464' is equivalent to '4464'. Here are some selling on eBay right now:-

D41464C-10 NEC DIP18 10NS

5PCS KM41464AP-12

Just be aware that these chips may be refurbished and possibly remarked with different parts numbers. Usually they are equivalent, but sometimes not (I bought some 'MCM2114P20 1kx4 SRAM' chips that are actually BU2114F 8 bit shift registers!).

A good way to generate randomness using discrete logic is to exploit the metastability characteristics of a flip-flop.

A D flip-flop is a type of flip-flop that has a clock (triangle looking input) and a data input (D input) as shown below. Normally, the state of the D input is transferred to the Q/!Q output one propagation delay after a rising edge on the clock.

(from http://www.learningaboutelectronics.com/images/D-flip-flop.png)

The data must "set up" a specific amount of time before the clock edge and "hold" a specific amount of time after the clock edge in order to assure that the input is correctly transferred to the output. If the setup and hold times are not met, then the state of the output at the normal propagation delay time for the flip flop becomes random. The randomness can be tuned by varying the frequency and phase of the clock and data and the amount of time that you wait to check the state of the output.

The graph below is from a TI paper that discusses the metastability characteristics of various 5V logic families. In general, the slower the logic, the worse the metastability and the more often random errors occur. This means that older logic families are more useful for generating random errors. The graph shows that using 74HC style logic, the error rate can be tuned from thousands of times per second to once per day by varying the wait time after a clock at which you look at the output of the flip-flop (tx). This specific graph is for a 1 MHz clock and a 500 KHz data input.

Note that metastability is delay, temperature, and voltage sensitive, so tuning to a specific event rate could be challenging. But it might be possible to build something good enough for your needs.

The test circuit from the TI paper is shown below. It can be a starting point to a random event generation circuit.