digital-logicttl
If you connect together two outputs from 7400 NAND gates, which output will dominate – high or low?
Background: I'm reverse-engineering a 1969 circuit board, and in multiple cases they tie together two outputs from 7400 NAND gates, presumably to make a wired-OR. This would be reasonable if they used open-collector chips, but these are SN7400N chips, so it seems a bit sketchy. (In other places, they leave an input floating, presumably to high, which also seems sketchy.)
Given the goals of the class, I think the TTL approach is fine, and I say this as an "FPGA guy". FPGAs are a sea of logic and you can do all sorts of fun stuff with them, but there's only so much that's humanly possible to do in a semester.
Looking at your syllabus, your class is a mix of the logic design and "machine structures" courses I took in undergrad. (Plus, it's for CS majors. I'm all for CS majors having to face real hardware--letting them get away with writing code seems like a step back.) At this introductory level, where you're going over how assembly instructions are broken down, I see no real benefit to having students do things in code versus by hand. Doing HDL means learning the HDL, learning how to write synthesizable HDL, and learning the IDE. This is a lot more conceptual complexity and re-abstraction. Plus you have to deal with software issues.
Generally the point of a course that uses FPGAs is to practice creating logic that is useful--useful for talking to peripherals, serial comms, RAM, video generators, etc. This is valuable knowledge to have, but it seems very much out of the scope of your course. More advanced classes in computer architecture have students implement sophisticated CPUs in FPGAs, but again, this seems out of the scope of your course.
I would at the very least devote a lecture to FPGAs. Run through a few demos with a dev board and show them the workflow. Since you're at Mills, perhaps you could contact the folks at Berkeley who run CS150/152 and go see how they do things.
The 74LCX07 will not clamp the output to \$V_{DD}\$ (the datasheet talks about \$V_{CC}\$), since its particularly targeted at interfacing between different supply voltages. Note that the inputs are 5V tolerant, also with \$V_{DD}\$ = 3.3V.
The datasheet says maximum output voltage is 5.5V (never use the 7V mentioned under Absolute Maximum Ratings), but should have mentioned for what supply voltage, for instance also for 3.3V.
The only characteristic I could find which actually indicates that a higher output voltage is allowed is off state current on page 4, which gives a value of 10\$\mu\$A at \$V_{CC}\$ = 2 to 5.5V and \$V_O\$ = 5.5V.
edit
That could have been clearer. Especially since it contradicts what it says under Absolute Maximum Ratings: "DC Output Diode Current, for \$V_O > V_{CC}\$: 50mA."
The NXP 74LVC1G07 seems to be a solution.
To level shift up from a 3.3V system to drive 5V CMOS input levels, simply connect the LVC output to a 5V termination voltage through a pullup resistor as shown below. The outputs of these devices are 5V tolerant and provide a simple solution to drive 5V CMOS input levels.
From here.
It also only mentions output clamping current for \$V_O < 0\$, so it won't clamp 5V.
Best Answer
The low one wins, TTL outouts have a stronger pull down than their pull up.
TTL inputs are current sources so they float high naturally.
when high there's 130 ohms and a diode between VCC and the output pin. that's going to limit the high-state output current to about 25mA
Combining outputs in this way will hurt performance, the device will produce more heat and probably be slower than if you used actual and gates to combine their outputs, bit if the main goal is to use fewer parts this can be a win.