I'm worried that I might have some impedance mismatch issues in my design.
I have an 8 layer PCB arranged as Sig-Gnd-Sig-Pwr-Pwr-Sig-Gnd-Sig except that the internal power planes have splits that run across the internal signal layers. So from an IO pad, a signal trace might cover 5mm over one power plane and 5mm over another before reaching a point where it can have ground planes on both sides, this is the worst case and many internal signals have shorter trips and/or only cross one plane.
Every signal trace has a continuous unbroken ground plane on one side but the internal layers have broken power planes on the other side. It's for a large BGA FPGA (a Stratix V) and the IO power pads are right in the middle of the IO signal pads so I'm a bit stuck in that regard. The tracks are all 0.125mm (~5mil) and every dielectric layer is 0.2mm (~8mil).
With clock rates be hitting 600-800MHz, am I likely to have any major signal integrity/impedance mismatch issues where the tracks cross the power planes?
This is for a hobby project so I can't afford to add more layers (the price goes up nearly 6x) or change track widths (not enough room). In order to route out all the IOs I need, each track is already at the minimum width the fab allows (with an impedance already a bit on the high side). Once out from under the chip the tracks transition to the correct width and will have unbroken ground planes everywhere. It's just the first 10mm under the chip where the tracks cross power planes I'm worried about.
EDIT: To everyone who suggested I change the stackup and or trace width/space, I'm not doing this as part of a commercial product, Euro circuits was the only fab (that I'm aware of) that would make an 8 layer board at a price I could afford (170 Euro for a 75x75mm panel), making the trace width/spacing thinner or changing the stack up would both push the price to nearly 1400 Euro for the same panel which is far more than I can afford to throw at this project.
Best Answer
What you can do is something roughly like this:
Minimize y and maximize x. Pick z to get 50 Ohms with a 4 mil trace on the inner signal layers. If x is much larger than z then the inner signal layers will be referenced more strongly to GND than they are PWR. If you don't need 50 Ohm traces (if you can accept lower than 50 Ohms), you can make the 2.5 mil and z mil dimensions even smaller.
You should find an online stackup calculator and play with it a bit. There are also constraints on total board thickness. The "standard" thickness is 0.063" which is more or less 1.6mm. If you deviate from this too much, it may make board assembly more difficult for the assembly house (check before you commit to doing it).