Electronic – Implementation of AES algorithm using Systolic architecture

algorithmencryptionparallelvlsi

I need to generate a VLSI Systolic array to implement the AES encryption algorithm with key length of 128 bits. Following are the possible ways :

Systolic for Key expansion
Systolic in MixColumn
Systolic for the on-the-fly calculation of S-box

For option #3, I am referring to this paper. Figure 2.1 from this paper gives the steps for calculating multiplicative inverse, which is the first step in S-box calculation. I am trying to convert this diagram into a systolic array, but haven't reached a concrete solution until now.

I am also referring to this paper to convert a cyclic algorithm into a Systolic one. However, I am not able to convert the operations involved in the AES encryption into Systolic structure. Could anyone give me any pointers on how to approach this problem?

Best Answer

There have been papers published on AES implementation using systolic arrays, e.g. "The AES in a systolic fashion: Implementation and results of Celator processor" (2008), but it does use some memory. Another is "An 8-bit systolic AES architecture for moderate data rate applications" (2009), basically a mix column design. Whether any of those approaches meet your other (rather unclear) design requirements, I don't know.

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Electronic – AES-128 Chip Solutions

Having a separate encryption co-processor could be risky. Anyone with a Bus Pirate or logic analyser and physical access can sniff the bus and pluck out the plaintext data.

You can mitigate the risk a bit with BGAs and/or epoxy, but the best solution is likely to be a SoC which combines MCU with AES.

One approach might be to use a SoC ZigBee chip and ignore the radio part, eg. CC2430, or EM250.

Or, you could go with a Stellaris Cortex-M3 (some have AES tables in ROM)

Or, do it in software. I've used Brian Gladman's code before in projects.

Electronic – Smallest AES implementation for microcontrollers

I'm wondering how did you get 7.5kB of RAM usage with axTLS. Looking at the code, all the context is stored in this structure:

typedef struct aes_key_st 
{
    uint16_t rounds;
    uint16_t key_size;
    uint32_t ks[(AES_MAXROUNDS+1)*8];
    uint8_t iv[AES_IV_SIZE];
} AES_CTX;

Size of this structure is 2 + 2 + 4 * 15 * 8 + 16 = 504. I see no global variables in aes.c, automatic variables are all small, so stack usage is also reasonable. So where does 7.5kB go? Perhaps you're trying to use the whole library instead of just extracting AES implementation from it?

Anyway, this implementation looks pretty simple, I'd rather stick to this code and try to optimize it. I know it can be tricky, but learning the AES details can help you at least to estimate the absolute minimum RAM usage.

Update: I've just tried to compile this library on IA-32 Linux and write a simple CBC AES-128 encryption test. Got the following results (first number is the section length hex):

 22 .data         00000028  0804a010  0804a010  00001010  2**2
                  CONTENTS, ALLOC, LOAD, DATA
 23 .bss          00000294  0804a040  0804a040  00001038  2**5
                  ALLOC

That's just 660 bytes of .bss (I've declared AES_CTX as a global variable). Most of .data is occupied by IV and key. I don't include .text here, as you'll get totally different result on PIC (data sections should be nearly the same size on both architectures).

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Related Solutions

Electronic – AES-128 Chip Solutions

Electronic – Smallest AES implementation for microcontrollers

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