Electronic – Implementing circuit with d-flipflop in verilog

circuit-designflipflopverilog

I'm fairly new to Verilog and I'm currently trying to do a structural implementation of a circuit that consists of an d flipflop, it has inputs x and y, x and y are exclusive or'd and that result is exclusive or'd with the current state, and used as the input to the d flip flop. and it'll use the result state from the flipflop in the next run, etc. But I'm not too sure how to construct it.

The circuit looks like so:

And my code is as follows:

module circ(clk,x,y);
 input clk,x,y;
 wire state=1'b0;
 wire xoy,d;
 xor(xoy,x,y);
 xor(d,xoy,state);
 dff a(d,clk,state);
endmodule

module dff(D,clk,q);
input D,clk;
output q;
reg q;
initial q<=0;
always @ (posedge clk)
 begin
  q<=D;
 end
endmodule

I'm pretty sure the d flip flop code is correct but when I try to test this my d and state values are just x for some reason. When I put in different x and y values in my testbench nothing happens, "state" and "d" just always says it has value "1'hx" in the simulation. Why is this happening and how do I actually assign an value to them?

I'm just not really understanding what you're supposed to do with the state, I'm assuming you need to give it a state at the very first run but if I give it a state isn't it just going to set state to that value every single time that module is accessed?

This is what state looks like on the simulation chart, it just stays red forever:

Best Answer

In your simulator, the initial value of the D flipflop is undefined, hence the behavior of your circuit is undefined. You can take one of two approaches:

Add an initial assignment to the flipflop:
```
initial q <= 0;
```
Add a reset signal to the flipflop, and toggle it from your simulation. Your always block should then be:
```
always @ (posedge clk) begin
    if(reset) q <= 0;
    else q <= D;
end
```

Related Solutions

Verilog inital value for flip flop

You are using c as an active high reset, then setting the value to c rather than 1'b0. It is active high so c is always 1 when this code executes. The solution to this is the reset condition to 0 not c:

always @(posedge clk or posedge c) begin
  if (c) begin
    x <= 1'b0; //Reset Condition
  end else begin
    //x <= ...;
  end
end

Your code makes use of an initial and asynchronous reset. This does not really represent any type of hardware you have to choose one or the other, you can not have both.

The waveform in the question does not show the async reset being applied at the start of the simulation. you should apply it for at least 1 clock cycle and release it on the posedge of your clock.

Beginner trying to understand flip flops

"What does it mean when a flip flop performs a function like SET, CLEAR, HOLD, or TOGGLE?"

Explanation for SET:From the name,it suggests that,when you apply Logic HIGH to 'S'(Set),this sets the output Q to logic HIGH.The not(Q) will be it complement(logic LOW)

Explanation for RESET:If you apply logic HIGH to 'R'(Reset),it makes the output Q to logic LOW,then not(Q) will be HIGH.(note that 'S' should be in logic LOW at that time).

Explanation for HOLD:If you apply Logic LOW to both input(S and R),The output doesn't change.I mean,it HOLDS the past output.

"I start with a clock signal that goes into each flip flop. From there, I really have no clue how to trace what's going on."

.In level triggering,The flipflop is ready to get the input throughout the Level of the clock continuous.In edge triggering,The flipflop will be ready to get input only when the edge of the clock is detected.Always edge triggering is preferred.

Best Answer

Related Solutions

Verilog inital value for flip flop

Beginner trying to understand flip flops

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