Electronic – Implementing dynamic frequency scaling on PIC32 by changing PLL multiplier/divider

low-powerpicpll

I read in the PIC32 Reference Manual that one can change the PLL multiplier and divider at run-time, provided that the input frequency is between 4 and 5 MHz and the resulting frequency does not exceed device specifications. Does this mean that one can use this to implement a dynamic frequency scaling scheme to save power (taking ino account PLL switching time and lock)

Thanks

Best Answer

Yes, you can switch the clock speed of the PIC32MX dynamically.

The easiest way is to use the OSCConfig call in the PIC32 Peripheral Libraries, since it switches the clock temporarily to the FRC mode before switching back to one of the other clock modes, including PLL. So you don't have to explicitly switch to FRC mode first, like you would have to do if you were writing directly to the clock mode fields. You do need to disable interrupts around the call though.

Here is an example:

    #include <p32xxxx.h>
    #include <plib.h>
       .
       .
       .
    INTDisableInterrupts();
    OSCConfig(OSC_POSC_PLL, OSC_PLL_MULT_15, OSC_PLL_POST_1, 0);
    INTEnableInterrupts();

The various constants are listed in the documentation for the OSCConfig call.

Danger, Will Robinson! The code example Microchip shows in their documentation is wrong, so if you cut and paste from the documentation, it won't compile! The example uses OscConfig instead of OSCConfig. The latter is correctly used in the rest of their documentation.

I found the documentation for the PIC32 Peripheral Libraries is in this document. Oddly, I couldn't find the PDF on the Microchip site. There is a compiled help file with the same information in the Microchip\MPLAB C32 Suite\doc folder, but I like the PDF better.

You don't have to install anything to use their peripheral library, as it comes with the PIC32 compiler. NOTE: I am using an older compiler, pic32-gcc.exe v2.01, so it is possible the call has changed, but I doubt it for compatibility with older code.

Related Solutions

Electronic – Can’t run PIC24EP128MC206 at rated speed

You should check out example 7-2 in the pic24E family reference manual (FRM) titled "Code Example for Using PLL with 7.37 MHz Internal FRC":

// Select Internal FRC at POR
_FOSCSEL(FNOSC_FRC & IESO_OFF);
// Enable Clock Switching and Configure Primary Oscillator in XT mode
_FOSC(FCKSM_CSECMD & OSCIOFNC_OFF & POSCMD_NONE);

int main()
{
    // Configure PLL prescaler, PLL postscaler, PLL divisor
    PLLFBD=63;            // M=65
    CLKDIVbits.PLLPOST=0; // N2=2
    CLKDIVbits.PLLPRE=0;  // N1=2

    // Initiate Clock Switch to FRC oscillator with PLL (NOSC=0b001)
    __builtin_write_OSCCONH(0x01);
    __builtin_write_OSCCONL(OSCCON | 0x01);

    // Wait for Clock switch to occur
    while (OSCCONbits.COSC!= 0b001);

    // Wait for PLL to lock
    while (OSCCONbits.LOCK!= 1);
}

It looks like the critical step you're missing is __builtin_write_OSCCONL(OSCCON | 0x01);

Also, looking at the math: 7.37*(76/(2*2)) == 140.03MHz which is slightly outside the allowed range, assuming that 140MHz is actually the maximum range (don't ask me why but for some reason it seems like it may be 120MHz).

If this still doesn't work then perhaps there's just an issue with your power supply. The internal FRC oscillator is unstable under temperature and voltage stress, so perhaps you should check to see if you have too much noise. This would make the FRC wonky as well as the VCO used in the PLL, preventing a lock.

If you look at table 30-18 in the pic24EP128MC206 datasheet, it tells you that over the temperature and voltage range you have about a ±1% for some models and ±2% for others. Figure 31-9 shows the variation with a stable voltage over a temperature range. There doesn't appear to be an analysis of voltage variation at a stable temperature.

If you're trying to get a stable run at a high frequency I would just grab a crystal.

EDIT (from comment): So from the sounds of your other posts about your conditions it sounds like you should look elsewhere for a problem. What's the frequency of the ripple? Did you size the internal Vreg capacitor properly? It sounds like since this is a locking issue and not a setting issue you're having some other problems with the board that aren't related to your code.

EDIT:

Glad this turned out to be the right answer! Good luck debugging the rest of the board!

Electronic – will two plls wander with shared reference clock

Not wandering from their reference is a PLL's entire purpose in life. Two of them that are locked to the same reference will not wander away from each other. There will be some phase noise / jitter that is uncorrelated between the two of them, but they won't drift apart over time as long as they both stay locked (as mkeith said).

Best Answer

Related Solutions

Electronic – Can’t run PIC24EP128MC206 at rated speed

Electronic – will two plls wander with shared reference clock

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