I am not up on the latest FPGA capabilities. What would be the lowest cost FPGA chip that can implement 1050 linear feedback shift registers of 71 bits each register?
The shift registers have to be independent and be configured for serial to parallel out. This does not mean I need an I/O for each tap, but the internal circuitry has to have the serial to parallel capability.
Best Answer
1024 registers times 71 bits requires around 72k flip flops. In some cases the synthesis tools will play tricks to get the size down, depending on the tap locations. If you specify how many taps, it may be possible to get a better estimate. On Xilinx devices, you can fit a shift register of up to 32 elements on one LUT, but you don't get any taps in there. Best case would be 3 LUTs per shift register for 3072 total, assuming the taps are between 24 and 32 bits apart. Xilinx Spartan 6 LX75 would work for the raw flip flop count, Spartan 6 LX9 would work for best case LUT packing. You should probably throw together an implementation of the shift registers on a large Spartan 6 and see how much space it takes up and go from there. For the 7-series devices, the Artix-7 XC7A15T would be large enough for best case LUT packing, or XC7A75T would be large enough for raw flip-flops.