Electronic – Implications of having duplicate case statement in verilog/system verilog design module

system-verilogverilog

Are there any implications if you have a design module as shown below where you have a duplicate case statement (duplicate case 2'b01 :)? As far as I known the execution is via precedence, so the second duplicate statement doesn't get executed. In terms of fabrication and any other reasons why this may not be ideal or it doesn't matter.

module jk_ff (input j, input k, input clk, output logic q); 
 always @(posedge clk) 
 case ({j,k}) 
 2'b10 : q <= 1; 
 2'b11 : q <= ~q; 
 2'b01 : q <= 0; 
 2'b01 : q <= ~q; 
 default : q <= q; 
 endcase 
 endmodule

Best Answer

The implications will show up when you get to a real project.

It will show up when you get into code coverage. It's one of many ways you can create unreachable statements. SystemVerilog has a unique case that flags multiple matching case items during simulation.

BTW, It's also a bad idea to have q <= q; statements—leave that behavior implicit. It gets in the way of debugging or what called backdoor access. You try to set a register when you don't think it's being used, and your setting gets overwritten with the previous value.

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