flipfloplatchreset
Here is the initial state of SR latch both reset and set inputs are zero.
Here we apply a pulse to the reset input and it shows it changes in this way
first –
and then –
The thing that I don't understand how R pulse can change Q state without receiving feedback signal from second NOR gate, and second NOR gate must receive feedback signal from first NOR gate which one of them happens first?
To rephrase the question: " how do you change the internal operation so that if S*R = 1 that only one of S or R is exerted"
That means you have to put some extra logic in there to control these signals.
Since this is homework and I don't do other's homework, I'll take you through the thought process.
If I want to control S so that when S*R=1 ir generate the control signal S'' = S + SR, S'' = S(1 + R) = S(1) = S so S'' = S so there is no logic to be put in there. Ooops, that clearly is the wrong signal to be playing with.
So that means that you need to block R' signal when S*R = 1. In other words, when S=1 do not allow R' to get to the input of the latch.
First a slight correction to your diagram. The NOT Q output is the output of the NOR1 gate, not the input you have shown.
When both inputs are LOW (0) the latch holds it state.
With S, R = 0, 0
If Q = 1, then NOR1 input is 0,1 and its output (NOT Q) is 0 keeping Q = 1 If Q = 0, then NOR1 input is 0,0 and its output (NOT Q) is 1 keeping Q = 0
i.e. NO CHANGE
If S = 1 (R = 0) then the output of NOR1 (NOT Q) will be 0 and the output of NOR2 (Q) will be 1 - the latch is SET, Q is HIGH
If R = 1 (S = 0) then the output of NOR2 (Q) will be 0 and the output of NOR1 (NOT Q) will be 1 - the latch is RESET, Q is LOW
The problem comes when both S and R inputs are taken HIGH at the same time and forms a race condition. This logical condition (S = 1, R = 1) is to be avoided as the output cannot be determined.
Best Answer
The truth table of a NOR gate tells you that the output will only be 1, if both inputs are 0. As soon as one input gets to logic 1, the output switches to a logic 0.
When R is set to 1, the condition of both inputs being zero is no longer fulfilled -> The output goes immediately low to 0. At this time the lower NOR gate still has to wait for the logic 0 to appear at its upper input - until than it will stay low. But as soon as the higher input sees the 0 from Q, the gate has two low 0 as input and will switch the output to 1.