Electronic – Internal and external clock synchronisation in FPGA

fpgavhdl

My FPGA has an internal clock of 66.66 Mhz. An input is a video signal clocked at the same frequency.

It seems that I can't clock a process processing the data with the internal clock, as I don't know about the phase of the signal, and the two frequencies may not be exactly the same.

I know that I can use a DPRAM to clock the video signal at the internal clock. I have also read that I can use two D latches to synchronise the two clock, but I don't get how it works.

I can't use the external clock because it can't be sure it will always be on.

Then, how can I process external data?

Best Answer

Look into clock domain crossing. There is a large body of knowledge on this subject. That said, on an FPGA you usually have 2 options:

  • Dual port fifo synchronization
  • 2 Stage register synchronization ( as you mentioned)
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