Electronic – Is it better to route Ethernet on the top layer, or to use vias

Good questions.

1) Does REF_CLK must be routed without vias.

Whenever you see something like "must be routed without vias" without a good explanation, chances are that someone does not fully understand what is going on and just think that is a good idea.

One of several things may be the issue:

• Different trace impedance on different layers, which will cause reflections whenever there is a via.
• Reference plane problem, because the impedance between the power planes of the design is not low enough.

Both of these are easy to avoid and is good practice - often even required if you want to pass EMI tests, build a solid design etc.

So provided you do this, you can use vias without any issues. The faster the signals, the more careful you have to design the vias. I have previously written about how to design vias for 28+ GBps signals here.

2) Does REF_CLK need termination resistor?

Best thing to do here is a quick simulation with your favorite IBIS simulator - or have someone do that for you (sorry, these tools costs money - but are worth it).

If you have very fast edge rates, chances are you need a termination resistor if the trace is electrically longer than about 1/3 of the rise/fall time. Use simulation to be sure (unfortunately you did not provide enough information about your design, or I might just have done it right away).

3) Is 4mm difference in trace length @50Mhz acceptable?

Another good question. Look at the rise/fall times of your signal. If the electrical length of the rise/fall time is significantly longer than the trace length mismatch, this will work just fine. Actually it is a good practice not to overconstrain layouts, even though it is often possible to match trace lenghts within a very narrow tolerance.

Things that spring to mind:

• usually, you'd model your PCB trace as transmission line that has exactly the same characteristics on the top, as on the bottom layer. As such, it doesn't make much of a difference where on the length of a trace you put the via; so instead of having these "looking like boobies" vias right next to each other, I'd just offset them enough to keep them in the middle of your trace
• R51, C5 could as well be on Top Layer
• I don't know the frequencies of your xtal or CPU, but chances are that the 125 Mbaud of Gigabit ethernet won't be much impressed :) however, if you're nervous about coupling, you might want to consider the classical star-like multiple ground-plane architecture. I don't think this'll be necessary here – Gigabit Ethernet Network PHYs aren't exactly bleeding edge in 2016, so even with some interference, they should work.
• just looking at the part of the layout I see, I'd say it might be easier to route if you just rotated the PHY by 90° – but that might break down the moment the complexity on the "processor side" of the phy comes into play.
• I think your RJ45-magnetics layout is OK; I'd probably been lazy and just routed the two diff pairs that are at the right half of the transformer "down" from the connector's pins, and the left half "up"; but that wouldn't have saved you from the one pair that crosses the other if you're supposed to access the magnetic's pads only from one side (unless you fit two traces between adjacent RJ45 pins...) . Topology is not always your friend :/

Notice: 1GE has a baudrate of 125 MBaud, i.e. even if considering the first two sidelobes, you really shouldn't be worried about frequencies above 375 MHz. With FR4 (with specific epsilon), and a lot of laziness approaching formulas, the wavelength of that frequency is roughly \$\frac15 \frac{c_0}{375\text{ MHz}}= \frac 15 \frac {3\cdot 10^8 \frac{\text m}{\text s}}{3.75 \cdot 10^8\frac1{\text s}}\approx \frac4{15}\approx 0.27\text{ m}=270\text{ mm}\$, so a 2mm trace length difference is but 2.7° phase error ... I think you'll be fine, even with a bit of unelegant routing.