Is MOSFET gate threshold voltage a limit or minimal “Full-on” switching voltage

Read your own question. The answer is obvious since it is embodied in the question.

You said yourself the gate threshold voltage is 2-4 V according to the datasheet. So how can 3.3 V on the gate possibly guarantee that the device is on? Clearly 3.3 V is less than 4 V.

You should also look more closely at what gate threshold really means. Note that it defines "gate threshold" as the gate voltage at which there will be 250 µA of drain current. That's unlikely to be a useful amount of current in your application, and is certainly not in any way the fully on state of the MOSFET.

Gate threshold is not a useful parameter if you want to turn the FET fully on. It tells you where it starts to turn on, not what it takes to turn it on fully, or full enough for your application.

The drain to source on-resistance is much more relevant, just a few lines in the datasheet below the threshold voltage. That is specified as 540 mΩ, but at 10 V on the gate. In other words, this FET is intended for 10 V gate drive to really want to turn it on. They aren't making any promises what happens between the threshold voltage and 10 V.

If you want to drive a FET with only 3.3 V on the gate, you have to get one specified for that. For example, the IRLML2502 is characterized at low gate voltages. The datasheet promises the Rdson will be 80 mΩ or less at 2.5 V on the gate, and 45 mΩ or less at 4.5 V. So one of those can be usefully driven from 3.3 V. In that case you know it won't exceed 80 mΩ and can support up to 3.6 A.

The threshold voltage can be increased if the source is not connected to the body terminal. The threshold voltage is

$$V_T = V_{T0} + \gamma\sqrt{2\phi + V_{SB}} - \gamma\sqrt{2\phi}$$

where \$V_{T0}\$ is the threshold voltage when the source-to-body \$V_{SB} = 0\$, and \$\gamma\$ and \$\phi\$ are device parameters. If the NMOS source is connected to ground and so is the body then \$V_{SB} = 0\$ and \$V_T\$ is minimized (it's a similar argument for the PMOS).

So, yes, it is possible to adjust the threshold voltage by not connecting the NMOS body to the negative supply and the PMOS body to the positive supply.

However, this is usually not done intentionally. You typically want to minimize \$V_T\$ -- for example, this would allow you to use lower supply voltages.

The body effect is particularly undesirable for a common drain amplifier because it lowers the voltage gain. Without the body effect the unloaded voltage gain of a common drain amplifier is

$$\frac{v_o}{v_i} = \frac{g_m}{g_m + \frac{1}{r_o||r_{oc}}} \approx 1$$

where the approximation assumes the resistances are large. However, with the body effect the unloaded voltage gain is reduced:

$$\frac{v_o}{v_i} = \frac{g_m}{g_m + g_{mb} + \frac{1}{r_o||r_{oc}}} \approx \frac{g_m}{g_m + g_{mb}} < 1$$