Could anyone help explain how the above 3T1C DRAM cell works? T means transistor and C means capacitor. Why is reading it not destructive?
Electronic – is reading the 3T1C DRAM cell not destructive
dramtransistors
Related Solutions
Due to the different topology and the fact that you're using tunnelling, NAND must be erased in blocks before being written to. This means doing writes becomes a two step process. The topology increases bit density but makes it more difficult to perform random accesses.
DRAM doesn't have this limitation, since it's just a capacitor, with basically a wire to it, you just charge and discharge the capacitor. There's no concept of erase before write. DRAM's topology also allows virtually random accesses so there's no penalty there when performing writes because you don't have to erase entire blocks.
Having to use quantum tunnelling for NAND doesn't help either.
NAND Flash 
DRAM 
Here's a picture that I hope will clear things up for you. Keep in mind that the result is not a 1 or 0, but a level that will be passed to a "sense amplifier" on the bit line.
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Best Answer
During a read T1 is off and T3 is on.
Then T2 controls the read line from the charge on the capacitor. Since it’s gate is very high impedance, no current is drawn from C to do that. That leaves C’s charge, hence the state of the bit, unchanged.
T2 is both the strength and weakness of this cell design. Yes, it makes readout nondestructive. But it also takes up significant space, increasing cost. As system design advanced to handle destructive reads, this design became disfavored.