biasmosfetresistors
I stumbled upon the following paper while looking for ways to calculate a specific value for the pullup/pulldown resistor for the gate of a MOSFET. I see several calculations for Rg. Is that the pullup/pulldown resistor for the MOSFET?
Related see this Q
Here is a quantitative way to determine the boundaries of acceptable gate termination resistance \$R_g\$ for power MOSFETs .
This will be a lazy lazy lazy (\$L^3\$) approach. So:
The intent of a (\$L^3\$) approach is get maximum insight/usefulness with minimum effort, by using a model that is simple as possible but still meaningful.
Model is a simple capacitive divider with resistive pull down. \$V_{\text{gs}}\$ was solved for in the frequency domain, and then inverse Laplace transformed for time domain.
Three operating conditions are analyzed using this model:
After setting \$R_g\$ = \$\infty\$:
\$V_{\text{gs}}\$ = \$\frac{C_{\text{gd}} V_{\text{ds}}}{C_{\text{gd}}+C_{\text{gs}}}\$
So, in this case, \$V_{\text{gs}}\$ is just a scaled version of \$V_{\text{ds}}\$, and the scale factor is the capacitive divider of \$C_{\text{gd}}\$ and \$C_{\text{gs}}\$. For the IRF510:
\$V_{\text{ds-max}}\$ = 100V
\$C_{\text{gd}}\$ = \$C_{\text{rss}}\$ = 20pF
\$C_{\text{gs}}\$ = \$C_{\text{ciss}}\$ - \$C_{\text{gd}}\$ = 135pF - 20pF = 115pF
\$V_{\text{gth-min}}\$ = 2V
For a drain to source voltage greater than 14V, \$V_{\text{gs}}\$ will be greater than the 2V threshold and the part will start to conduct. It doesn't matter how the voltage appears on the drain, just that it is there. Pretty obvious why nobody ever leaves a FET gate unterminated.
Allowing \$R_g\$ to be a variable finite value:
\$V_{\text{gs}}\$ = \$C_{\text{gd}} V_{\text{dsSlp}} R_g \left(1-e^{-\frac{t}{R_g \left(C_{\text{gd}}+C_{\text{gs}}\right)}}\right)\$
\$V_{\text{dsSlp}}\$ is the slope or linear ramp forcing voltage (in volts/second) across the drain to source. If \$V_{\text{ds}}\$ rises from 0 to 25V in 2 milli-seconds, \$R_g\$ will need to be less than 11 MOhms for \$V_{\text{gs}}\$ to remain below the 2V threshold and remain off.
Such slow rates of change (in the 1 to 10 milli-second range) for \$V_{\text{ds}}\$ are why Olin Lathrop can correctly say \$R_g\$ values of 1kOhm, 10kOhm, or 100kOhm ought to work. So, yes for a passive pull down to keep a FET off during system startup or other seldom switched low dV/dt application, almost any kilo-Ohm resistor will do.
Why even waste time looking at this? If that's all there is we can all just roll over, go back to sleep, and be happy. But, there's a lot more to it, so let's look at a little of that next.
Nearly all FETs end up being frequently switched, between 10KHz and 500KHz, with short rise and fall time \$V_{\text{ds}}\$ transitions. Most FETs will be turned off in 20 to 100 nano-seconds, and this is where gate termination becomes important. Let's look at the IRF510 with \$V_{\text{ds}}\$ rising linearly from 0 to 25V in 50 nano-seconds. Using the equation in conditon 2 above:
\$V_{\text{gs}}\$ = \$ \text{(20pF) }\text{(25V/50nsec) }\text{Rg} \left(1-e^{-\frac{\text{50 nsec}}{\text{(20pF + 115pF)} \text{ Rg}}}\right)\$
So, plugging in a value of 270 Ohms for \$R_g\$ gives \$V_{\text{gs}}\$ ~ 2V. That would be the highest value of \$R_g\$ that could be used without the FET possibly turning back on.
\$R_g\$ greater than this maximum value allows the FET to be turned on a little or a lot, depending on the energy forcing \$V_{\text{ds}}\$. FET could turn on just enough to leak current and dissipate power, but showing no real effect on \$V_{\text{ds}}\$, or could turn on enough to cause \$V_{\text{ds}}\$ to drop, which in the right conditions can cause oscillation.
Clearly, the higher the peak value or transition rate of \$V_{\text{ds}}\$ the lower the gate circuit resistance must be.
Why not just make \$R_g\$ zero, or as small as possible?
So far in this analysis, the gate circuit is dominated by resistance, but there is also inductance in the gate circuit. If gate resistance is minimized, gate inductance becomes dominant in circuit dynamics, and with \$C_{\text{gs}}\$ forms an LC resonant circuit. LCR circuits with Q > 1 become increasingly ringy, which is a problem for FET gate control if charge is injected through \$C_{\text{gd}}\$ from \$V_{\text{ds}}\$ or also from switching waveform from the gate drive . For example, an LCR circuit with a Q of 2 will ring to about 1.5 times its driving voltage. For a gate drive with a 14 V source, a Q of 2 would be enough to damage the gate of most FETs.
For a series LC resonant circuit :
Q = \$\frac {Z_o} {R}\$ and \$Z_o\$ = \$\sqrt {\frac {L} {C}}\$
Let's look a a specific case with the IRF510. Including routing and package inductance, the gate circuit could easily have 11 or 12 nH of inductance. Recall that the IRF510 has a \$C_{\text{gs}}\$ of 115pF, so \$Z_o\$ would be about 10 Ohms. Matching \$R_g\$ to \$Z_o\$ would give a Q of 1, which would be the maximum Q for non-overshoot of drive waveform. Minimum \$R_g\$ should be greater than \$Z_o\$.
Consider this to be the minimum knowledge needed about gate circuit resistance in MOSFETs.
The gate resistor on a MOSFET is really there to protect whatever is sourcing the current. Much like a discharged capacitor, the gate will initially look like a short to ground when voltage is first applied. A MOSFET with a very large gate capacitance can sink a very large amount of current for a short period of time. If you're driving the gate with, say, a MCU pin, it's usually a good idea to put a small resistor to reduce that current surge to a value the MCU can handle. If your MCU pin can handle, say, 20mA and you're driving 3.3V into the gate, then you choose a resistor that limits the current to 20mA at 3.3V:
$$R_{gate}=\frac{V}{I}=\frac{3.3V}{20mA}=165Ω$$
The digital output pins of most MCUs are current limited already, so this isn't strictly necessary. But why pound on the output drive circuitry to the point that the current limiter kicks in?
Incidentally, MOSFET drivers are ICs specifically made to drive a large amount of current into the gate of a MOSFET so as to turn on the MOSFET as quickly as possible. The MOSFET turns on quicker and the switching losses are less.
All of that said, I believe you have another issue with your circuit. I suspect 3.3V is not enough to turn on two UV LEDs in series. The voltage will need to be at least as high as 2x the foward voltage of one of those LEDs. As it is, I don't think the LEDs will turn on.
Best Answer
The lecture deals with DC steady state analysis of the MOSFET. Pull-up and pull-down play the role when there is switching or transient behavior.
I wouldn't call RG1 and RG2 in the lecture pull-up and pull-down. In the lecture, they form a resistor divider, which sets the gate voltage. They may have as well drawn an ideal voltage source between gate and ground.