Electronic – Is the dielectric layer under the top or bottom copper layers always prepreg or can it be a core

In general, I would say keep the top-side pour; it certainly does no harm, and it has some secondary benefits, such as less etching required and less thermal stress on the board during reflow.

You do still need to pay attention to current loops and place the vias appropriately, not just scattering them about randomly. Since the FT232R is the only active chip on the board, focus on its outputs. There are two LEDs that are powered by V_USB, and a few outputs associated with the serial port that are powered by V_CC. Where do the currents flow when any of these outputs change state? Try to keep the paths as short and direct as possible.

Note in particular, the ground path for the USB connector in your non-pour example. It has to go down, cross below the chip, then come up on the right before it gets to the ground pins on the top of the chip. The top-side pour shortens this considerably. In either case, it would help if you adjusted the vias near pin 1 of the chip so that the bottom pour is continuous there.

One side point about your design: Try to avoid having three etches come together at an acute angle, like you have on your Vcc trace. Make that a right-angle tee connection.

Difference between core and prepreg is that core has cooper filled on both sides of dielectric and prepreg is just full dielectric, no copper on any side of the material.

Since you just sandwiched the prepreg between two cores, which are themselves clad with copper, the prepreg now has copper on both sides of it.

Why wouldn't return current flow on the top side of CORE between SIG-GND since there is a full cooper plane on top side of CORE?

High frequency return currents for layer 1 (SIG) will mostly flow on layer 2 (GND). Just how you want it.

High frequency return current for layer 4 (SIG) will mostly flow on layer 3 (PWR). Making this work well likely requires having good bypassing near all source and load locations for high-speed signals.

Return currents for PWR will indeed flow in the GND layer, because those two layers are separated by just the few mil of prepreg. If there also large ground fills on layer 4 you will also get substantial return currents there, even more so if the core layers are much thinner than the prepreg layer.