ddrddr2ddr3layoutpcb-design
BGA DDR packages have a unique footprint. There are two columns of pads on both sides of the device, and an empty column in between.
Is there a reasoning behind the placement of these pads (in terms of PCB layout), or is this just a consequence of the design of the ddr3 silicon die?
More specifically, what I am wondering is, are there any tips/tricks/guidelines to place DDR modules on both sides of the board, directly across, or very close to each other?
If the part is SMT your best bet is probably to try to put a fairly intact ground pour under the chip (bottom layer) and route most of the traces out of the dense area on the top layer. The power connections can be tied together and bypassed to ground with ceramic capacitors near the chip on the top or under the chip on the bottom. Of course there will be vias near the capacitors either way.
If it's through-hole, it may make more sense to try to route some traces on top and some on bottom, again with bypass capacitors near the chip. A ground pour on the bottom and a Vdd pour on top may make sense, though neither will be very much like a multilayer power plane.
Today's circuits tend to have a lot of different Vdd/Vcc voltages, and sometimes Vee if you're doing mixed signal designs, so a complete power plane covering the entire board is a bit of a dream even with 6 layer boards, let alone two layer.
Perhaps the answer is simply historical carry over maintaining pin compatability (originally going back to the '08' chip - 1K ROM).
Compare the pinout with is its much older cousin the 2716 (EPROM) - a 24 pin chip. In the 'good old days' this was the basis for developing a lot of the earlier microcomputers.
When more address lines were needed (A11 - A15) they fitted them into the extra pins. Pin 28 was designated for power so the original pin 24 (now = pin 26) was available to connect an extra address line (A13) leaving A8 and A9 and A10 in their original positions. Vpp (programming voltage on old pin 21 was not required) so this became A11 (new pin 23). This left new pins 1,2 and 27 to assign to A15, A12 and A14.
This effectively allowed older 24 ROMS and EPROMS (and RAM chips such as the 6116) to be plugged into the later (28 pin) designs.
As regards PCB traces (I'm assuming your using at least double sided) there is no problem with the order. You are simply connecting pin 1 to pin 1, pin 2 to pin 2 etc. by taking the (horizontal) trace between pins, remembering you have both sides of the board to play with. If you require the address bus in a particular 'order' bring out the horizontal traces from the memory block and use vias and perpendicular traces to re-order them.
Best Answer
You can take a look at a DDR3 die and Xray photo of the same chip here : http://chipworksrealchips.blogspot.com/2011/02/how-to-get-5-gbps-out-of-samsung.html
You can see that the memory is organized along a central spine and that the pad are placed along this spine. I can't tell you more about the internal layout as it's not my field of expertise.
For DDR PCB layout you can read this Application Note :
For the chips' placement it's more a signal integrity issue as the timings are sensitives. If your PCB and process technologies allows you any placement and your design is compliant with DDR/DDR2/DDR3 standard (mostly timing constraints) you are free to go with it.
I haven't seen a board with DDR3 memories for the moment, I only worked with a board with DDR2 chips. The five chips were placed on the same side (same or opposite side of the CPU) and side by side.
I can only recommend you to simulate your DDR design to be sure that your placement and routing are ok.