Since it is typical propagation delay, and it is 74LS86, I will have to use the table on the typical Column with the 86 “2 levels” row right? And how do I get on from here? Correct me if I’m wrong please. I can’t seem to figure out how to calculate.. Thank you
Electronic – Is this the correct way of calculating the typical propagation delay
delay
Related Solutions
"Contamination delay" seems to be a new term for what we old-timers used to call "minimum propagation delay". It's the minimum time from when the input crosses its first threshold to when the output crosses its first threshold.
Similarly, "propagation delay" is what I would call "maximum propagation delay". This would be the time from when the input crosses its final threshold until the output crosses its final threshold.
There may be different numbers for high-to-low and low-to-high transitions.
I'm not sure why your diagram shows different threshold levels for inputs vs. outputs. Perhaps that's intended to account for noise margins within the circuitry.
For the first transition, with the output going high-to-low:
- tPHL(MIN) = 80 ps (contamination delay)
- tPHL(MAX) = 180 ps (propagation delay)
For the second transition, with the output going low-to-high:
- tPLH(MIN) = 60 ps (contamination delay)
- tPLH(MAX) = 100 ps (propagation delay)
When accounting for propagation delays through a chain of logic, you have to assume that any given node is "undefined" between the two delay values for a given transition.
Added: The increased information shows that a solution is possible using this IC with somewhat reduced functionality - mainly delay being limited to a restricted range under "automatic" voltage control with coarser steps being applied manually.
The comments which the OP made re VC using circuits from page 17 of the data sheet are highly appropriate.
This very simple circuit and annoyingly complex relationship from fig 10, page 17 of the data sheet, does indeed show an essentially complete solution across a limited delay range. The expression is reducible to one of the form
t_delay = k1 / (k2-Vc)
ie delay is inversely proportional to the inverse of the difference between a fixed voltage and Vc.
This could be refined to delay proportional to control voltage with more external control circuitry. ie
by varying Rset effective so that Iset tracks Vcontrol you get linear delay control with voltage. Rset is effectively replaced with a voltage control voltage source. This can be further expanded on if desired.
Larger steps in delay may be provided by switching V_DIV in Vcc/16 steps.
The material below is still correct but less relevant to the reduced range requirement.
The delay from a LTC6994 can be set to a predetermined value in the range ~= 1 uS to 33 seconds by both
Applying a calculated voltage to the DIV pin and
Connecting a predetermined resistance from ground to the SET pin
or drawing an equivalent sink current from the SET pin.
To vary the delay in response to a varying voltage is very much harder as the delay can be swept over only a 16:1 range with SET-pin sink-current variation, and must then be stepped by a multiple of 8 by
incrementing the voltage on the DIV pin by a 1/16th Vcc step, and simultaneously
decrementing the sink current out of the SET pin by a factor of 8
and starting again.
There are a number of other ways of meeting your described requirement which may be better than this one. Knowing what you actually want will help with proposed solutions. See below.
The LTC6994 will potentially* do what you want, but only with additional control circuitry and some "head scratching". The IC achieves control using two variable analogue inputs - it has a ~= 16:1 current controlled sweep range, plus a voltage controlled programmable divider whose division ratios increase by a factor of 8 at each step (1 8 64 512 ...). This means that achieving a required division ratio is somewhat akin to "juggling priceless eggs in variable gravity". ie to get smoothish variation with increasing Vin, as Vin varied you'd need to increase i_set by a factor of 8:1, then increase Vdiv by a step of Vcc/16 while decreasing i_set by a factor of 8 and continuing. "Steps would occur". Also - from 1 to 8 us you get 1 uS/delta-V change, from 8 to 64 uS you get 8 uS per delta-V change, from 64 to 512 uS you get 64 uS per delta V change, ...
A more complete specification may help us give you a better solution. Telling us what you actually want to do rather than asking if a solution meets your essentially unknown to us need is liable to get better results.
Do you want a smoothly varying delay with voltage?
What resolution and accuracy do you require?
What response time and settling time?
What ... ?
If you are prepared to control it with a microcontroller you could achieve relatively transparent control using a single input control voltage. Otherwise it would be "challenging" [tm].
The formulas and notes on page 11 of the datasheet make it clear that
The basic delay is variable from 1 uS to 16 uS
The delay is based on a controlled current, not a voltage.
(You can use a VV to make a VC but effectively the IC wants to see a variable resistor to ground at the "SET" pin and applies ~= 1V to it to create the desired current.)
The IC then scales the above 1 - 16 uS delay by a factor of
Division ratio = 2^(3 x (Vdiv / Vcc)) where Vdiv = voltage on Vdiv pin.
ie it establishes a 4 bit (16 level) value from Vdiv,
uses 1 bit for polarity
and uses the other 3 bits to select 1 of 8 division ratios
with ration increasing by a factor of 2^3 = 8 each time.
= divide by 2^3x for x = 1 2 3 4 5 6 7 8
= divide by 1 8 64 512 4096 32768 262144 2097152
The smallest delay is thus 1 uS x 1 = 1 uS and
the largest = 16 uS x 2097152 = 33.55443s
This diagram, from the data sheet, shows how I-set controls the delay over a limited range and how a voltage controlled divider then multiplies that delay.
*-Pun noticed :-)
Best Answer
The trick to this question is understanding how an XOR is constructed. V.V.T had the correct answer.
The blue path is the longest when "A" is low, the leftmost NAND output is high regardless of the "B" input.
The red path is the longest when "A" is high.
I can't find any documentation that indicates that this is how a 74LS86 is constructed, but a NAND gate is a basic building block for TTL so it is likely. I am guessing that this gate implementation is buried in the textbook somewhere, or was included in datasheets back when this textbook was written (old textbook).
image from: https://en.wikipedia.org/wiki/XOR_gate (annotated by me)
Edit: Here is a spec from a TI 74LS86 datasheet. The numbers don't match what the OP posted, but the fact that the prop delay is dependent on the state of the other input is clear. I admit that the NAND implementation is a guess, but in any case, there are 3-levels of gates, transistors or whatever; and one of them is bypassed when the other input is low.
https://www.ti.com/lit/ds/symlink/sn54ls86a.pdf