# Electronic – JFET stabilised wien bridge component ratios

jfetoperational-amplifieroscillatorwien-bridge

I find myself in need of a sine wave oscillator and have decided on the wien bridge. I have followed all the tutorials but have a few questions that do not seem to be answered elsewhere.

Firstly, I understand the ratio between Rf and R3 determines the negative feedback loop gain set to 3, or just above, at a ratio of 2:1. But there are lots of combinations of resistances which would give that ratio, so what effect would say using a 1 OHM : 2 OHM resistance be compared to 10 OHM : 20 OHM? And the same question about the capacitor resistor combinations in the lead lag circuit.

Second, how do the values of Rf and R3 get selected when there is a JFET paired with R2? I figured that to get a gain of 3 after the gate voltage comes up then I would add the Rds(on) of the JFET to R3 and count them as one, so then when the JFET is off, there would be no resistance through it and the gain would be higher than 3, allowing oscillations to start. Is this correct? Any particular ratio between the JFET Rds(on) and R3, does one dominate, equal or does not matter?

Third, the negative peak detector which drives the gate of the JFET charges a capacitor, which has a resistor in parallel. What is that resistor R4 doing and how is its value determined? How is the capacitors value determined?

Lastly, what determines the output voltage? Say, I need a 0.1 v output to feed a BJT amp, what values would I need to change and how would I calculate them? I figured the output would be determined by the maximum peak to peak printed on the datasheet, but how would I bring this down?

Thanks for any replies

#### Best Answer

Regarding the control loop Diode-C3-R4:

This is not a peak detector because the parallele resistor R4 continuously discharges the capacitor which - in turn - is charged by the output amplitude (if it can open the diode at a certain level). This is necessary in order to allow amplitude control in BOTH directions. The opamp gain swings around the nominal value of "3".

Hence, the output amplitude is NOT CONSTANT - it will exhibit a small amplitude modulation which is determined by the time constant C3-R4. This time constant should be at least ten times larger than the oscillation period. From this requirement you can select both values (C3 and R4).

Regarding the ouput amplitude: An exact computation is not possible (due to the nonlinear Diode characteristics). However, a good estimat is possible if you know the nominal value (during steady-state oscillations) of the FET resistance and the corresponding gate voltage. This give you the mean voltage across C3 and - together with app. 0.5 across the diode - a reasonable guess for the corresponding output amplitude.

EDIT (error correction): There is a logical error on your side.

You wrote: .....when the JFET is off, there would be no resistance through it and the gain would be higher than 3, allowing oscillations to start.....

No, when the JFET is off the RDS resistance is very large and the opamp works as a unity gain amplifier (full feedback).

The correct description is as follows: At t=0 the ouput voltage (and the gate voltage) is zero and the FET is open - the RDS resistance is low (max current ID) and the gain larger than "3". Now - for rising amplitudes the gate voltage becomes more and more negative and the RDS resistance goes higher and provides more negative feedback (the gain is decreased until it reaches "3").