I have the circuit below using PIC16F627a, which should support ICSP (drawn in autocad instead of built in editor). IO pins which are not relevant to my question are omitted.
Outputs RB5 and RB6 have to be fed back to inputs RA5 and RA6 respectively. Those signals named 'reset' and 'inhibit' need to be combined with corresponding signals of identical units in two global signals for the whole system. All reset signals are logically ANDed, because all units have to agree on a global reset. Inhibits are logically ORed, because a single unit should be able to initiate this function.
As can be seen, 12V programming voltage would be fed back to output RB5 via diode D2, possibly damaging the PIC. To eliminate this danger, a 2k2 resistor R1 is included in the system, limiting the current that could flow back to RB5.
A similar concern may apply to IO pair RA6/RB6 but only when ICSP CLOCK voltage is low would RB5 be pulled to ground. I don't see any inherit dangers here, the diode used here is just to play it safe.
Will this simple solution applied to VPP eliminate the danger of getting 12V on RB5, destroying the IC?
Note: the additional units inside the cloud are to enhance to IO capacity of the system.
Best Answer
2.2k will still allow quite a bit of current to flow and could push up the power supply rail on the chip.
I suggest using an NPN BJT wired-or rather than a diode to force /MCLR low (reverse the output logic on B5). I'm not sure the clock is an issue- it's not high voltage.