I'm currently designing a carrier board on which is integrated a PLX PEX 8750 PCIe switch connected to several PCIe connectors.
The problem occurs when routing PCIe lanes, since I can't route them without having to “criss-cross” the lanes. Thereby, I consider using the lane reversal capability.
The PEX 8750 supports dynamic Lane reversal as mentioned on its datasheet, but it also indicates that "If the wiring of Lanes to a device is reversed (on both Transmitters and Receivers), only one of the two connected devices must support Lane reversal."
I also read a paper published by Intel which says: "Unless you are certain that lane reversal is supported and guaranteed by at least one of the devices in question, do not rely upon this feature."
Taking Advantage of the PCI Express Specification – EDN
So, which of the two sources should I believe?
Best Answer
According to section 4.2.4.10.1 of the PCIe 3.0 Base Specification:
So according to that second point, either the Downstream of Upstream device can reverse the lane order.
Later on, in section 4.2.6.3.2.2, it discusses example cases for lane reversal. In the main example, it is written:
Interpreting this further, as long as at least one of the devices supports lane reversal a link can be established.
If lane reversal is needed, and the upstream device (closest to the RC) is capable of doing it, then it will always be the one to do the reversal regardless of whether or not the downstream device supports it.
The link process is something like:
The downstream port tells the upstream port its preferred ordering.
The upstream port will try to match that request
The downstream port will check what lane mapping the upstream port is echoing.