Electronic – Lattice MachXO2 reset

fpgalatticeresetverilog

After reading about GSR/PUR facilities in Lattice FPGAs, I'm still a bit puzzled about how to actually get the proper GSR/PUR-based reset functionality on an actual physical FPGA chip.

In the How to Use GSR and PUR application note, they show this Verilog example:

GSR  GSR_INST (.GSR (<global reset sig>));

suggesting that .GSR corresponds to an input, thus <global reset sig> would be mapped to an external pin (as I understood it).

But then, how do I use the output of that GSR_INST ? I distinctly remember that they say that the reset is active-low given the underlying circuitry. However, in the HDL Coding Guidelines, page 38/39, they show (Verilog version):

reg[1:0] state;
reg dout;

always @(posedge clk or posedge rst)
    if (rst) begin
        state <= idle;
        dout <= 1'b0;
    end
    else begin
    case (state)
    // ยทยทยท

That rst looks like an active-high reset signal (otherwise the code wouldn't make sense / wouldn't work). So, is rst a reserved keyword that corresponds to the output of the GSR_INST, and it is implicitly available anywhere I need it?

In short: how do I put the pieces together? (taking advantage of the GSR functionality, that is). I'm ok with or without automatic/implicit power-up reset (I can externally assert the reset pin of the FPGA for a few milliseconds after power-up). But I would still like to know about how to set it up both ways.

Best Answer

The wire/signal passed to the instantiation of the GSR module just tells Lattice Diamond that that signal is the signal that should use the resource-saving GSR hardware. You can call it whatever you want. There is no output of the GSR module; it's not a buffer or something.

You can also pass nothing into it, e.g., GSR GSR_INST (.GSR ());, so it's a) simulatable (sometimes Diamond/Active-HDL throws errors if you don't instantiate a GSR block in your design, even if you're not using it) and b) an option for later. I've done this so it doesn't slip my mind but before my reset scheme is totally nailed down.

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