I don't think a foot or two of wire connecting digital signal wires mandates very much design considerations. The current flow in digital signals is so low and your wire length is so short that inductive effects are negligible. Likewise, there will be virtually no loss to the wire resistance. And with very small current flow comes very little radiated energy, so you shouldn't have to worry about generating EMI. There's always a danger of absorbing EMI from nearby devices (the wire acts like an antenna), but I doubt that will be a problem for your situation.
The main consideration I would think about is the danger of ESD events on the wires. The mere presence of the wires off the boards increases the chance of contact with charged objects (most likely your hands) that can send transient voltage spikes down the wire and into both boards. For that reason, you never want to connect the pins of the microcontroller or other sensitive components directly to a connector that goes off-board. At a minimum, for digital lines, I would recommend a resistor in series with the connector and an ESD-rated TVS (Transient Voltage Suppressor) diode to ground. And that feeds into a digital buffer IC, which, finally, connects to the pin on the microcontroller. The resistor can be any large value in the kiloOhm range and the TVS diode should have a breakdown voltage a little higher than the digital high voltage on the lines.
You can get much more sophisticated with ESD protection, but that should give you "good enough" protection.
It's difficult to answer this without all the details, but here is a generic look at the problem which I believe may also be the more useful type of answer for this site.
Multi-node-nets should always be simulated. They are so difficult to predict. And it took about 3 minutes to see that your design was maybe not optimal.
Here is the simulation setup for the clock from the master to all the slave devices (values are just rough estimates, as would be the case if you did this before building anything):
And the resulting simulation plot (we ignore what is what, units etc. as it obviously is not worth building):
The first idea that comes to mind is a daisy chain of all the inputs and a simple parallel termination. A fly-by scheme if you want. This looks like this in the simulation setup:
And the result plot looks a lot nicer:
If you can live with the increased power consumption of the thevenin termination and the reduced voltage swing on the clock inputs of the various devices and... (only you know the actual constraints)... then some variation of this may actually be worth building.
There are other solutions that would work, but the key is to understand that multi-node nets are not easy to predict. The 5 minutes of simulation here before you build something can save a lot of time later. Unfortunately this type of simulators do not come cheap.
I am using Cadence SigXplorer here. The usual disclaimer apply: I do teach classes in signal integrity and often have Cadence or Mentor sponsor software licenses for those classes.
Best Answer
If the signal Trise and Tfall are 10:1 longer than the time-of-travel along the PCB path (and the wiring path), you do not need controlled-impedance design. [Note some people use 20:1. ]
What this means is: with 100 nanosecond Trise and Tfall, the electrical length of the trace/wire can be 10 nanoseconds (about 5 feet), if standard FR-4 (with Er of 4.5) is used. People will debate about using one-way or round-trip delays.
Also read this answer: Distance between SPI traces to prevent cross talk
Note I edited this (about 5 feet) is correct, since sqrt(4.5) for FE-4 is ratio of 2.2 slower than speed-of-light. Thus 5 feet of PCB trace, atop FR-4 where most of the energy is in the underlying FR-4 and NOT up in the air, becomes 2.2X longer or 11 nanoseconds. I use 1 nanosecond/foot as good working number.