I asked Xilinx for such a list but they don't have a complete list. I wish to make sure all input files are in source control and all output files aren't. This is with 13.1-13.2 with ISE and PlanAhead
Some of the information they have provide is the list of PAR Output Files and the ISE Design Suite Files in the Command Line Tools User Guide, the source files list from here.
Edit Aug 19 2011: mentioned 13.2 and PlanAhead
Edit Sep 7 2011: removed EDK reference since some in answer