Electronic – Logic gates that does not need to to tie to 1 k resistor and ground open inputs to drive it low

Yup. That's a classic, all right. One of the interesting characteristics of the 7400-series TTL logic family is that an open input behaves like a logic HIGH. It's not good practice to do this, since such unused inputs can act like antennas and start picking up noise, but it's working just fine in your case.

In your circuit, tie each input to +5 with a 1k resistor. When you want to drive that input LOW, just ground it.

And since you're just starting, you need to start developing good habits. That means do not leave any inputs on a chip floating. You can usually get away with it with TTL and LSTTL, but it will drive you crazy if you do it with CMOS. In this case, tie all 6 unused inputs of the 7408 together, and tie the whole thing to +5 with a 1k resistor.

Also, get a 0.1 uF ceramic capacitor, and connect it between pins 7 and 14. This is called a decoupling, or bypass, capacitor, and for more complicated circuits one capacitor per IC is a very, very good idea, with each capacitor connected right to the power and ground pins of its' IC. It doesn't have to be a high-voltage capacitor, since it will only have 5 volts on it.

As already commented by John D, a real schematic would definitely help readers.

However, there is one clear bug:
There is no connection from IC pin 7 to Gnd (0V). Please add that and re-test.

Update: I'm not 100% sure of my interpretation of some of the wiring related to Gnd connections (the wiring is just missing off the top of the photo). However it seems that you have connected IC pin 11 to Gnd. That would be correct for an unusual 5420 package (military temperature version of 7420 in a ceramic flat-pack) but is not correct for a standard 74LS20 in "N" package (plastic DIP) like yours.

I wonder if you have misinterpreted whatever IC datasheet you have been looking at, if it contains that (unusual) 5420 pinout, with Gnd on pin 11?

From the TI datasheet, the 74LS20 pinout for "N" (plastic DIP) package is as shown immediately below. Notice that pin 11 is "NC" (Not Connected) - not Gnd; the correct Gnd is pin 7, as I explained earlier, and that Gnd connection to IC pin 7 is missing on your breadboard:

Whereas in a "W" (ceramic flat-pack) package, the 5420 uses pin 11 as Gnd:

A couple more points:

• Since it doesn't have the correct Gnd connection, the IC is currently being powered using a "phantom" Gnd, perhaps through the LED. This won't be doing the IC any good, although I hope that permanent damage won't happen.

• Your design uses a TTL NAND gate output (pin 6) as a current source for the LED. That is not the best way to drive loads like LEDs, since TTL ICs can "source" much less current (on that IC, TI list a maximum of 0.4mA) than they can "sink" (on that IC, TI list a maximum of 8mA).

  Your LED will be drawing more than 0.4mA from that output pin and so it will be exceeding the output's recommended maximum "source" current - not good for reliability.

  Instead, either add a transistor to that IC output to drive the LED; or use the IC output to "sink" the LED current, although this will invert the LED lighting logic compared to what you expect. It would probably be clearer if you research terms like TTL LED driver, or similar. See this answer for some examples of TTL outputs "sinking" LED current.