Electronic – Low cost FPGA and EDA tools? costs

Until recently, 500 MHz would have been considered a fairly fast clock, requiring a relatively high-end (and high-cost) FPGA. But nowadays a low-cost part ought to be able to do that.

However, there are other specs that are equally important to the data rate to determine what part will work for you:

• What's the data width? A 16-bit adder requires a longer carry chain than an 8-bit adder and so requires a longer clock period in a given architecture and speed grade.

• How many taps in the filter? A very large number means working with RAMs instead of just registers, leading to a new set of timing requirements and new considerations for which parts will meet your needs.

• What are the weights? Equal weights on all taps means a much simpler calculation. If you have different weights on each tap, you might need to redo the complete set of add-multiplies for each new input sample, making for a much harder problem.

But if your other specs aside from clock rate are fairly relaxed you might be able to do this in a low cost device.

• All the FPGA vendors have low-cost FPGA lines that can be priced as low as $5 each. For example, Xilinx has Spartan and Artix, Altera has Cyclone, etc. In recent generations, these parts should be able to do at least minimal logic at 500 MHz. But if you have to do wide add-multiplies or something, you may have to do some very careful pipelining or other tricks to get them to work. Be sure to look at the most recent generation of parts to get best performance, best pricing (unless a family is absolutely brand-new), and longest assurance of supply.

• Recent CPLD's from Altera and Lattice are really small FPGAs with built-in flash to allow automatic reconfiguration on power-up. For a simple filter, these might be sufficient.

But without knowing your complete design we can't tell you what device will work. You'll have to just try designing it for each candidate part and use the vendor's synthesis tools to find out if you can meet timing in each case.

These are defined in details in the document:

LatticeXP2 Family Data Sheet

If you go down to "Table 2-1. Resources and Modes Available per Slice" you will find the detailed description of how these slices are used and what kind of terminology they use when reporting the usage of them.

Let me know if this is OK, or I add more data to the answer to clarify it further