Electronic – Low-power “killswitch” until power reset

latchlow-powerpowerpower supply

I have a specific design issue and do not know how to start. We have a supply of about 9-13 VDC, battery-powered. The circuit I'm looking for acts as a power switch for this supply voltage. By default, it should be closed. When a 3.3 V "kill" signal is asserted, however, the switch should sever the connection and latch this "killed" state until all power is removed (then at next turn-on it should be default closed again). It is critical that the power consumption in the "killed" state is as low as possible (ideally less than 10 µA).

My thought on this so far: I'm looking for a P-channel MOSFET to do the switching, with a large resistor pulldown on the gate (1 MOhm between G and GND). MOSFET S goes to power in, D goes to power out. I need some sort of low-power "latching" circuitry now that overrides the "default on" state, probably by using bipolar transistors (to ensure they don't accidentally fire on power up, i.e., driven by current not voltage). Once engaged, they would pull the G to S. But I do not know how start this, any hints?

Edit: I have put a draft of my idea in LTspice, but power consumption in the "killed" state is way too high, about 11 mA:

LTspice schematic

Best Answer

Here is an alternate latch circuit based on standard logic gates.

R1-C1 form the power-on-reset that forces the circuit into the closed state. A 3 V Kill signal latches the output off by turning off the voltage translation transistor Q1. R3 ensures that the MOSFET is completely off. for a more "firm" turn-off, decrease it to 10K.

When the output is off, the circuit static current should be in the uA range, just the static current of the two gates. There is no off-state current through any of the resistors.

NOTE: Instead of AC series CMOS, use single-gate low voltage devices such as the Picogate series from Nexperia. TI has two gates in one package: https://www.ti.com/product/SN74LVC2G132

NOTE - Schematic is incorrect; gates should be NOR's. Update coming.

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