There are some open questions, but I'll take a stab at answering. I'll assume you want voltage control of a load that must be ground referenced, the voltage range is 0-45V, a 48V supply is available, the maximum current is 1A, and the control input is a voltage from 0-5V.
Here is a circuit that fullfills the requirements I stated:
This is similar in idea to Russell's circuit with a few key differences. Q2 is a controlled current sink linear with the opamp output voltage in the range of about 600mV to 5V. This current variably turns on PNP transistor Q1. The opamp output from about 600mV to 5V maps linearly to the load current, which should help stability. The compensation cap C2 working against R2//R5 provides a means to add additional stability as needed. C2 shouldn't need to be more than a few 10s of pF.
With 5V on the base of Q2, the emitter will be about 4.3V, so Q2 will sink 70 mA. Assuming the power transistor Q1 has a gain of at least 15 (in the plausible range for this type of transistor), the load current can be up to 1A.
R2 and R5 divide the load voltage into the 0-5V range the opamp can handle. Since stuff happens, you want to make sure all is OK with the full 48V at P1. This 48V divided by R2 and R5 becomes 4.75V into the opamp. That's close enough to 5V to use most of the range but still leave a little margin.
You will have to think about the power dissipation of Q1 carefully. It could be quite a lot depending on what current your load really draws. Worst case the load voltage is half the supply, so 24V, and drawing 1A. That puts 24W on Q1, which is quite a lot. If your load really can draw up to 1A, then Q1 probably should be a TO-3 with a good heat sink and forced air cooling. If that's too much, you need to consider switching topologies to accomplish what you are doing. 24W is not trivial to deal with.
Q2 could also get toasty, but nowhere near as bad as Q1. At the maximum of 5V on it's base, it will drop about 43V at 70mA, which is 3W. That's not too hard to deal with, like a TO-220 with a small heat sink. Of course if your load doesn't really need 1A this all scales down linearly.
Oops:
I updated the schematic to get rid extra resistor in series with the opamp negative input. The circuit evolved as I was drawing it and I didn't notice this resistor was no longer needed when the circuit was posted originally. The description has been updated accordingly.
Looks like a self-oscillating converter, probably a primary winding, a feedback winding and a secondary winding (6 pins). It would be similar to this, but with many more turns on the secondary:
I think this is a blocking oscillator with the transformer primary in the emitter of the transistor and the feedback winding blocking the base voltage.
The transistor is probably a cheap high-current BJT such as an 8550 with a base resistor and nothing else. The blue capacitor and the brown film capacitor form a voltage doubler (there is room for parts for more multiplication, but they're not populated). The two resistors are to discharge the capacitor- one is a 22M and the other is a 20K. When they use the tripler configuration they probably use two 22M or a 22M and a 10M resistor. Th
The LED is just across the input power (after the tact switch) with a resistor in series.
These things have to make with BOM adding up to not many pennies, so everything is minimized. The output capacitor is probably being run at way over rated voltage, the transistor will probably burn out if you hold the switch down, the transformer insulation is unsuitable for anything but brief momentary operation. Minimalist, fully Muntzed, design philosophy.
Best Answer
This reduces ripples in the power supply. Current is drawn from the 12 V supply in pulses. C2 reduces the impedance of the supply at the switching frequency, thereby reducing the voltage excursions caused by the current pulses.
No, it's a plain old comparator circuit, just that there are two of them. Note that each of the comparators U3C and U2B have the same inputs. They will therefore produce the same outputs. The positive input comes from a reference voltage produced by the pot labeled "50%", then filtered by R10 and C7. This is meant to be a fixed DC level, adjusted so that ultimately the desired DC level is achieved after rectifying the transformer output.
I haven't looked it up, but from the circuit it seems clear that the comparators have open collector outputs. Multiple comparators with outputs wired together therefore perform a AND function. The comparators U4D and U1A produce pulses of opposite polarity to ultimately drive the push-pull switching elements. The outputs of U3C and U2B simply ground these signals, thereby keeping the switches off, when the feedback signal is above the threshold.
This question makes no sense since MOSFETs are transistors.
The circuitry between a comparator output and its FET gate is a crude FET driver. It takes the open collector output of the comparator and drives the FET gate with it actively in both direction.
When the U4D output goes off, it goes up due to R1. That is at the high impedance of 10 kΩ, which would switch the FET slowly. Q3 is used in emitter follower configuration, and acts as a impedance buffer. It reduces the 10 kΩ drive by its gain. If the gain of Q3 is 100, for example, then the FET gate is being driven high by about 100 Ω instead of the original 10 kΩ.
That works for the rising edge, but does nothing for the falling edge, which would only drive the FET gate low due to R2. D1 fixes this by allowing a direct discharge path for the FET gate charge when the comparator output is actively driven low.