Electronic – LTSpice: how to pass to a function a component name as parameter

functionltspicesubcircuit

Good morning all.
I am implementing a subcircuit in LTspice, and I want also to modify the plot.defs to calculate some quantities with the voltages/currents inside the subcircuit. Thus, I will have a function like:

.func A(x) V(x:Vo)/V(x:Vin)

where the function "A" should take the instance name of the subcircuit as parameter, in order to access to its nodes (labelled Vo and Vin in the subcircuit, using a behavioral voltage source to make the node name always the same).

The syntax written above doesn't work, I get the error:

undefined symbol in: "A(<>)"

Where of course "X1" is the name given by spice to the instance of my subcircuit.
What could be the problem? Please note that by explicitly writing the expression of "A" in the plot panel, everything works fine, so it is a matter of how to pass the instance name as parameter.

Thanks all in advance!

Best Answer

There are two problems here, I couldn't get a user defined function to work in the graph. The other one is your trying to make a function that passes in a parameter, when you can only use them to pass numerical information.

The other one is you can't reference a pin current anywhere but a graph, so if your using the colons, that won't work. The way to reference a pin current is described in a few answers like this one. The short answer is if you want to reference a pin current is with a zero ohm resistor or 0V voltage source and then measuring the current (ie: for a resistor called R2, you can do this I(R2), but not this I(R2:1))

You can't use use user defined functions graphically, you can use them in b sources and other areas in the spice file. If the need arises where a function needs to be graphed, use a b-source to convert the function to data that can be graphed. Inconvenient, but that's the way it is, and is unlikely to change do to the way LT spice works.

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Electronic – VHDL functions with generic or “run time variable”, synthesis issues

Synthesis tools work very hard to evaluate everything at compile time that they possibly can. For everything else, they synthesize logic -- including function calls, assuming that the function is synthesizable (some are not).

Therefore, the answer to your question is, "it depends". It doesn't matter if the actual parameter to the function is a generic or a signal (port) -- if the value is known at compile time, the synthesis tool will evaluate the function at compile time and use the result. The only difference is that a generic is by definition known at compile time, while a signal may or may not be.

If the function needs to be evaluated at run time, then the synthesis tool will generate the logic required to do that, assuming that no non-synthesizable constructs have been used in the body of the function.

Electrical – How to enter .subckt model in Ltspice

For most simulators the first line in any spice file should be an asterisk *, and is always a comment line.

I do not think you should put the R= part in the resistor definition lines. The lines should work fine like this:

R<rname> <node1> <node2> <r_value>

For example:

RR1 1 3 'CR1+CR2*cos(CF1*pi*V(2,3))'

If this does not work, try defining the expression as a parameter first:

.PARAM R1VALUE='CR1+CR2*cos(CF1*pi*V(2,3))'

then define resistor values like:

RR1 1 3 R1VALUE

Also, it looks like in LTspice the .ends should have the subcircuit name afterwards, i.e.:

.ends SET

For particular nuances of each simulator check the documentation.

Best Answer

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Electronic – VHDL functions with generic or “run time variable”, synthesis issues

Electrical – How to enter .subckt model in Ltspice

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