Electronic – LTspice simulation problem when changing the load

ltspiceswitch-mode-power-supply

I have this simulation. I tried to do a simulation for observing cross regulation problem:

Here are the results:

The two outputs are equal and stable which is normal.

Nevertheless when I change the load on one secondary, it is completely unstable. I must always have the same loads to have stable outputs. I do not understand why it happens.

———-EDIT————————————————————–

SHEET 1 884 680
WIRE 560 -272 384 -272
WIRE 656 -272 624 -272
WIRE 800 -272 656 -272
WIRE -96 -256 -432 -256
WIRE 96 -256 -96 -256
WIRE 384 -240 384 -272
WIRE 656 -240 656 -272
WIRE 800 -240 800 -272
WIRE 96 -208 96 -256
WIRE -432 -192 -432 -256
WIRE -96 -192 -96 -256
WIRE 384 -112 384 -160
WIRE 656 -112 656 -176
WIRE 656 -112 384 -112
WIRE 800 -112 800 -160
WIRE 800 -112 656 -112
WIRE 656 -96 656 -112
WIRE -432 -80 -432 -112
WIRE 560 -48 384 -48
WIRE 656 -48 624 -48
WIRE 800 -48 656 -48
WIRE -96 -32 -96 -128
WIRE 96 -32 96 -128
WIRE 96 -32 -96 -32
WIRE 384 -16 384 -48
WIRE 656 -16 656 -48
WIRE 800 -16 800 -48
WIRE 96 0 96 -32
WIRE 224 0 96 0
WIRE 96 32 96 0
WIRE 48 48 -128 48
WIRE 224 48 224 0
WIRE -128 64 -128 48
WIRE 48 96 16 96
WIRE 384 112 384 64
WIRE 656 112 656 48
WIRE 656 112 384 112
WIRE 800 112 800 64
WIRE 800 112 656 112
WIRE 656 128 656 112
WIRE 96 208 96 112
WIRE 224 208 224 112
WIRE 224 208 96 208
WIRE -128 256 -128 144
WIRE 16 256 16 96
WIRE 96 256 96 208
FLAG 656 128 0
FLAG -432 -80 0
FLAG 96 256 0
FLAG -128 256 0
FLAG 16 256 0
FLAG 656 -96 0
SYMBOL ind2 80 -112 M180
WINDOW 0 36 80 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName L1
SYMATTR Value {Lmag}
SYMATTR Type ind
SYMBOL ind2 400 -32 M0
SYMATTR InstName L3
SYMATTR Value {Lmag}
SYMATTR Type ind
SYMBOL TVSdiode -112 -192 R0
SYMATTR InstName D1
SYMATTR Value TVS
SYMBOL diode 240 112 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D2
SYMBOL sw 96 128 M180
SYMATTR InstName S1
SYMBOL voltage -128 48 R0
WINDOW 3 -305 273 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 10 0 {transient_time} {transient_time} {D/freq} {1/freq} {Nbcycles})
SYMATTR InstName V1
SYMBOL diode 560 -32 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D4
SYMBOL cap 640 -16 R0
WINDOW 3 -91 54 Left 2
SYMATTR Value 1µ Rser = 1m ic = 0
SYMATTR InstName C1
SYMBOL res 784 -32 R0
SYMATTR InstName R2
SYMATTR Value 15R
SYMBOL voltage -432 -208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 50
SYMBOL ind2 400 -256 M0
SYMATTR InstName L2
SYMATTR Value {Lmag}
SYMATTR Type ind
SYMBOL diode 560 -256 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D3
SYMBOL cap 640 -240 R0
WINDOW 3 -91 54 Left 2
SYMATTR Value 1µ Rser = 1m ic = 0
SYMATTR InstName C2
SYMBOL res 784 -256 R0
SYMATTR InstName R1
SYMATTR Value 15R
TEXT 136 -104 Left 2 !K L1 L2 L3  1
TEXT -448 -504 Left 2 !.model sw sw ron = 10n roff = 10meg vt =0.5 vh = -0.5
TEXT -440 -400 Left 2 !.param freq = 100k D = 0.2 Nbcycles = 500 transient_time = 1/(2*freq*1000)
TEXT -440 -368 Left 2 !.param Lmag = 100u Lleak = 1p Coupling_factor = sqrt(1-Lleak/Lmag)
TEXT -448 -480 Left 2 !.model d d ron = 10n roff = 10meg vfwd = 0.7 vrev = 1k epsilon = 0.1 revepsilon = 50n
TEXT -448 -456 Left 2 !.model tvs d ron = 0.1 roff = 10meg vfwd = 100 vrev = 100 epsilon = 1 revepsilon = 1
TEXT -448 -320 Left 2 !.tran 0 {Nbcycles/freq} {(Nbcycles-50)/freq}

Best Answer

There are a few quirks you should know about simulators, in general: they are number crunching programs and, as such, they work with a finite underlying precision; in this case, double. Regarding precision, it is advisable to avoid too many orders of magnitude difference between adjacent variables (and not only) in the matrix solver. For example, using 10n = 10e-9 and 10Meg = 10e6 next to each other (in the .model for the VCSW and the diode) means the difference between those values is 1e15, which is sensibly close to 2.22e-16 in the case of double. Changing Ron=10m is a much better choice. If you're worrying that those 10m might influence negatively your simulation, don't, the values are small enough even for a real-life case; the influence will be so small it would not be perceived. But, if you're that worried, try 10u...100u, it should suffice even for sub-unity loads. The same for the diode's revepsilon, 50n -> 50m (epsilon and revepsilon model the quadratic regions for the diode, greatly helping convergence).

So the solution is to replace those three values. What you saw was the effect of an ill-conditioned matrix, which somehow worked in the first case, when the two secondaries were identical and, thus, the matrix solver could (presumably) make some simplifications, but not in the 2nd case, when everything needed to be treated separately.

There's one thing you should know: the coupling factor. You are explicitely using k L1 L2 L3 1, despite declaring Lmag and Lleak as .params (but you knew that, didn't you?). However, LTspice internally limits k to ±0.999'999 (whithin float precision). Your chosen values for Lmag=100u and Lleak=1p translate in a coupling factor of sqrt(1 - Lleak/Lmag) = 0.999'999'995, which is beyond the limit. This doesn't affect the simulation, just so you know that it won't work as you think it should.

Two last mentions: the number of cycles for the PULSE() source is not a mandatory parameter, so it can be omitted, and the .model card for the VCSW specifies vt=0.5 vh=-0.5, which means that the thresholds will be at 0 V and 1 V. But the driver swings from 0...10 V, which is useless for level=1. If the level is not specified, it defaults to 1, otherwise, the level=2 VCSW is never fully on or fully off, because the transfer function involves a hyperbolic tangent -- which also means that the derivatives are continuous everywhere.

Related Solutions

Electronic – LTSpice D flip-flop not working

If you go to the LTspice help and navigate to "Special Functions" you'll see a list of parameters that can be selected for the digital components, including the Dflop.

Your shift register didn't work because it had no output rise or fall time associated with it, so everything was happening all at once!

Also, the digital stuff defaults to a Vcc of 1 volt.

I've redrawn your schematic so everything starts cleared, Vcc is 5 volts, and put some delay into the Dflops, and now it works. :)

If you right-click on any of the dflops, that'll bring up the attribute editor, which will show their edited (non-default) parameters, specifically:

SpiceLine = Vhigh 5 Trise 10n

and will allow you to modify any of the component's editable attributes.

Here's the schematic and the plot, which I edited to look like a timing diagram:

and here's the circuit list:

Version 4
SHEET 1 1732 752
WIRE 48 -144 -256 -144
WIRE 352 -144 48 -144
WIRE 656 -144 352 -144
WIRE 864 -144 656 -144
WIRE 1104 -144 864 -144
WIRE 1360 -144 1104 -144
WIRE 1616 -144 1360 -144
WIRE -128 -64 -368 -64
WIRE 176 -64 -64 -64
WIRE 480 -64 240 -64
WIRE 784 -64 544 -64
WIRE 864 -64 864 -144
WIRE -256 0 -256 -144
WIRE 48 0 48 -144
WIRE 352 0 352 -144
WIRE 656 0 656 -144
WIRE 1104 0 1104 -144
WIRE 1360 0 1360 -144
WIRE 1616 0 1616 -144
WIRE -368 48 -368 -64
WIRE -336 48 -368 48
WIRE -160 48 -176 48
WIRE -64 48 -64 -64
WIRE -32 48 -64 48
WIRE 144 48 128 48
WIRE 240 48 240 -64
WIRE 272 48 240 48
WIRE 448 48 432 48
WIRE 544 48 544 -64
WIRE 576 48 544 48
WIRE 1024 48 736 48
WIRE 1280 48 1184 48
WIRE 1536 48 1440 48
WIRE 1728 48 1696 48
WIRE -336 96 -368 96
WIRE -128 96 -128 -64
WIRE -128 96 -160 96
WIRE -32 96 -128 96
WIRE 176 96 176 -64
WIRE 176 96 144 96
WIRE 272 96 176 96
WIRE 480 96 480 -64
WIRE 480 96 448 96
WIRE 576 96 480 96
WIRE 784 96 784 -64
WIRE 784 96 752 96
WIRE 1024 96 992 96
WIRE 1280 96 1248 96
WIRE 1536 96 1504 96
WIRE -368 208 -368 96
WIRE 992 208 992 96
WIRE 992 208 -368 208
WIRE 1248 208 1248 96
WIRE 1248 208 992 208
WIRE 1504 208 1504 96
WIRE 1504 208 1248 208
WIRE -256 288 -256 144
WIRE 48 288 48 144
WIRE 48 288 -256 288
WIRE 352 288 352 144
WIRE 352 288 48 288
WIRE 656 288 656 144
WIRE 656 288 352 288
WIRE 1104 288 1104 144
WIRE 1104 288 656 288
WIRE 1360 288 1360 144
WIRE 1360 288 1104 288
WIRE 1616 288 1616 144
WIRE 1616 288 1360 288
WIRE -368 336 -368 208
WIRE -256 336 -256 288
WIRE -368 448 -368 416
WIRE -256 448 -256 416
WIRE -256 448 -368 448
WIRE -368 512 -368 448
FLAG -368 512 0
FLAG 864 -64 0
SYMBOL voltage -368 320 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 3 86 297 Invisible 2
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 1u 5n 5n 0.5u 1u)
SYMBOL voltage -256 320 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 3 86 297 Invisible 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 0 50n 50n 100n)
SYMBOL Digital\\dflop -256 0 R0
SYMATTR InstName A1
SYMATTR SpiceLine Vhigh 5 Trise 10n
SYMBOL Digital\\dflop 48 0 R0
SYMATTR InstName A2
SYMATTR SpiceLine Vhigh 5 Trise 10n
SYMBOL Digital\\dflop 352 0 R0
SYMATTR InstName A3
SYMATTR SpiceLine Vhigh 5 Trise 10n
SYMBOL Digital\\dflop 656 0 R0
SYMATTR InstName A4
SYMATTR SpiceLine Vhigh 5 Trise 10n
SYMBOL Digital\\dflop 1104 0 R0
SYMATTR InstName A5
SYMATTR SpiceLine Vhigh 5 Trise 10n
SYMBOL Digital\\dflop 1360 0 R0
SYMATTR InstName A6
SYMATTR SpiceLine Vhigh 5 Trise 10n
SYMBOL Digital\\dflop 1616 0 R0
SYMATTR InstName A7
SYMATTR SpiceLine Vhigh 5 Trise 10n
TEXT -352 480 Left 2 !.tran 0 30us 0

Electrical – Measuring phase difference – LTSPice simulation problem

The D flip-flop is working as expected, but your simulation has other issues:-

the LT1716 comparator is much slower than the uA710 (~3us switching time vs 20ns). At 20kHz this slow switching causes noticeable pulse timing distortion. To improve accuracy you need to lower the input frequency (to eg. 2kHz).
Your digital logic blocks are set at their default logic levels of 0-1V (compared to ~0-3.5V for TTL) so the output amplitude will be lower than in the original circuit.

Note that the uA710 has TTL compatible outputs, but with a negative supply the LT1716 will pull below ground (which is not compatible with most digital logic families). It only works in LTspice because the simulated logic has no input voltage restrictions.

Other issues are shared with the original circuit:-

No resistor between the flop-flop output and 2N2369 Base. In a real circuit this would probably stress the flip-flop and increase saturation voltage of the transistor.
The 2N2369 has a fairly high saturation voltage which affects the output when it is turned on. It should be replaced with a low saturation type such as FTZ849.
When the transistor turns on it reconfigures the associated op amp from inverting to non-inverting mode, but also lowers the impedance at point E which reduces the signal voltage. This can be fixed by inserting a unity gain buffer amp between the output of the low pass filter and the 2x 15k resistors.

Best Answer

Related Solutions

Electronic – LTSpice D flip-flop not working

Electrical – Measuring phase difference – LTSPice simulation problem

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