Is it possible to have an input, say a button, that does one positive edge clock pulse? So I want to press this button once and it does a 0->1->0. I can't think of anyway to do it because it changes twice with one input.
Electronic – Making a positive edge clock pulse with a button
buttonclockpulse
Related Solutions
I've done this on multiple products to give a short pulse on the reset line once, no matter how long the button is pressed. In my case VDDS is a 3.3V rail, and nRESET is the reset line to the MCU.
Start with power on, button not pressed (open).
a. nRESET is pulled high through R1.
b. C26 has 0V across it.
When button is pressed, the node of R4 and C26 is grounded.
a. Since the voltage across a capacitor can't change instantaneously, C26 will pull nRESET low as well.
b. C26 will begin to charge through R1. The time it takes C26 to charge will be dependent on the value of R1 and C26. This RC time constant as well as the IC's VIL threshold will determine the low pulse time. The voltage across C26 will eventually charge to VDDS as long as the button is held.
When the button is released, the node of R4 and C26 will be pulled up to VDDS through R4.
a. This will cause nRESET to try to jump up to VDDS + the charge across C26 (which is VDDS). This would be 2X VDDS, which may exceed the voltage rating of the IC. This is the reason for D1 to clamp the voltage at nRESET to a safe level.
C3 is present to provide high frequency decoupling of the nRESET line, and may or may not be needed, depending on the application.
As mentioned above, tuning of the timing of the reset pulse can be accomplished through changing the values of R1 and C26.
The naming scheme on the primitives in your image suggests that this design is intended to be implemented in an FPGA.
If this is the case, gating a clock network is not recommended. Clocked logic elements in an FPGA can usually only be clocked by dedicated clock networks. These networks are only available in very limited numbers (i.e, perhaps a dozen on the entire chip!). Instantiating logic which passes a signal from combinational logic to a clock will typically result in one of these networks being used for that signal, making it unavailable for other logic on the chip.
To avoid this, most FPGAs will make logic primitives available with separate combinational logic "enable" signals. (Xilinx calls theirs FDCE/FDPE/FDRE/FDSE depending on the state at reset, and Altera calls theirs DFFE.) These logic elements will (more or less) AND the clock signal with the combinational enable signal, giving the same result as your schematic here without the detrimental effects on clock networks.
Best Answer
A single clean pulse can be created using a latch circuit, (cross coupled gates). Ideally this works best with a switch or push button having a SPDT format.
Another option is to use a SPST switch with (debounce) filtering which is basically an RC filter followed by a Schmitt trigger circuit.
One more idea is a one shot circuit using a chip such as a 555 series timer. With a 555 design you can even set up the desired pulse width.
Here is a Google link showing several of the above mentioned designs:
https://www.google.com/search?q=switch+debounce+latch&biw=1174&bih=600&source=lnms&tbm=isch&sa=X&ved=0ahUKEwir_tSHvpDLAhWE5iYKHWoLCM8Q_AUIBigB#imgrc=_