I couldn't find any info about this. Is there a general rule or does it change for all vendors(altera or xilinx)?
Lets assume I have a flip flop and I want to wire 10 flip-flops to its output. Normally, in my university lab using cheap (1$-2$) ICs, 10 was max value. Maybe same for FPGA? Or can it carry heavy loads like 2000 flip-flops wired to same output? Is this related to "drive strength" mentioned in verilog/vhdl? They dont mention a constraint.
In future, when I have an FPGA, I will try some floating-point compute accelerator that need to broadcast a variable to all cores.
As "Dave Tweed" commented, it must be "fanout" and he says its an implicit control by design tool. Any more info? How many gates are dedicated if it is implicitly driven?
I'm addressing inner (dynamic) parts of fpga which I will build some cores. Not the outer parts.
Thank you for your time.
Best Answer
You can send a signal on to many many other destinations (the number of destinations is called the "fanout" of the signal). The more destinations it goes to, the longer your critical timing path potentially becomes though, so the fmax of your design may suffer.
The tools will usually replicate the logic that drives those many nets if the timing becomes slower than you have requested in order to try and meet your timing target.
For Xilinx, this list of appnotes offers advice for reducing fanout when this is on your critical path (http://www.xilinx.com/support/answers/9410.html)