Electronic – Maximum frequency for a FPGA-based square wave signal

digital-logicfpgafrequencyhdlxilinx

I have an understanding problem what is the maximum possible frequency for a square wave signal that can be generated.

I am currently experimenting with a FPGA board (Red Pitaya), which has a 125Mhz Xilinx Zynq FPGA. When I am connecting the clock signal via a Binary Counter and Slice (Xilinx IPs) for the bit #0 and to an output pin, I measure about the half frequency (62,5Mhz).

Here is the Xilinx Vivado block diagram
(32bit Binary Counter in UP-mode, 1bit Slice Din From + Din Down To are both 0):

I would have expected that I will see exactly the clock frequency on the output port.

Can someone please explain me why the frequency got halved and what is the maximum square wave frequency that can be created by a FPGA?

Best Answer

You can't generate a frequency higher than the internal clock. If you have access to a Phase Locked Loop or PLL, you might be able to.

Usually the external clock gets fed into an PLL and the internal clock is generated from that.

If your internal clock is 125Mhz and your using a regular counter (counting on only the rising edge), the fastest counting you will see will be at half of 125Mhz or 62.5Mhz.

Counters can be built that work on the rising and falling edge to give you counting at 125Mhz

Related Solutions

Electronic – Pipelining and clock frequency issue

Your design will not function correctly if it runs at 100 MHz but is only spec'd (by the tools) to run at 50 MHz. If it does, then it's a one-off miracle that wouldn't work when you make a change and rerun the tools. Don't do it. Don't even do it if your clock is 100 MHz and the tools tell you the design can run at 99.5 MHz.

To solve your problem you can either write a simple 'divide by power of 2' clock divider to reduce the clock frequency (something like this in Verilog):

reg [n:0] count; 

always @(posedge CLK_100) begin
  count <= count + 1;
end

BUFG bg_0 (.I(count[m]), .O(CLK_DIV));

(where 'm' <= 'n' and 'bufg' is a global clock buffer, and must be used for synchronous designs) or use a Digital Clock Manager (DCM).

Hopefully that solves your pipelining issues as well unless you absolutely have to run the entire design at 100 MHz. Other than pipelining you can consider using FIFOs if you have part of the design running at 50 MHz and the other at 100 MHz, but you'll have to say a bit more about what you're doing to get more meaningful help here.

Electronic – How to create a square wave signal with 120MHz

Just add a Schmitt trigger to get a square wave from a sine.

Best Answer

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Electronic – Pipelining and clock frequency issue

Electronic – How to create a square wave signal with 120MHz

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