An ADC has a source synchronous output interface and is to be interfaced with an FPGA. The ADC can communicate using single ended CMOS, DDR CMOS and DDR LVDS. How do I know what is the fastest rate that I can run this at with the FPGA I have, assuming that the FPGA is the limiting factor.
These two FPGAs are being compared:
I believe that I just need to look at the fastest rate that the FPGA I/O pins can be run at. But, obviously the FPGA fabric will also need some attention. How can I find a ball park figure?
Best Answer
Option 1: Build your design and synthesize it with appropriate constraints and see if timing closes.
Option 2: Gain sufficient experience with a particular product family to have a good idea how complex a design can be run at a given frequency.
That said, if the I/O pins can handle a given data rate, there are techniques such as parallelization that should allow you to handle that rate in the fabric, at the expense of increasing the number of logic blocks used.