Electronic – Memory mapping in the 8085 microprocessor

In the history of microprocessors the start was with very slow processors and very fast memory (a 6502 did a fetch, then execute, and in the execute phase the memory was free to be used for other purpsoes, like DMA or video generation). The Z80 had similar 'idle' period in the instruction execute that could be sued for DRAM refresh.

With the generation of the 8085 the controller could just about finish an instruction before the memory was ready for the next memory cycle, hence the execution time does not show in the timing graphs.

After this the situation got more confused. On the one hand the controllers got faster, so the bus timing became totally dominated by memory access. But on the other hand controllers started to implement much more complex instructions like multiply and divide, which do show up in the timing. And the addition of caches and pipelining make everying even more confused.

The 8085 has different instructions for accessing main memory and I/O 'memory'. In addition to the standard memory interface pins the 8085 also provides a pin that identifies whether a memory access cycle is accessing main or I/O. This extra line is used in the select logic of both main and I/O 'memory'.

But there is no law that I/O can only be accessed by I/O instructions: in a small system the highest address line could be used to distinguish between memory (a15=0) and I/O (a15=1), so we get 32Kb for real memory (ROM and RAM) and 32 Kb for I/O.

Note that it is even possible to use the I/O addresses to access RAM, but that is less useful because there are only 256 I/O addresses and the addressing modes available for these addresses are very limited.