Electronic – Micro controller reset due to noise, PCB design for noise immunity

That's the Cypress FX2LP USB microcontroller (I recognize it because I use it myself). If you're using the Hi-Speed USB transceiver, then you should really go with a 4-layer board. Without that ground plane right below the top layer, it will be near impossible to get the 90 ohm differential impedance that you want for the USB D+/D- lines.

http://www.cypress.com/?id=4&rID=34128 flat out states that 4 layers is required. It also states that controlled impedance is required, but in my experience you can usually get away without it, so long as you carefully research your fab's typical stack-up and work out the right width, space, and height.

http://www.cypress.com/?docID=25406 also provides more info on calculating the width, space, and height for the D+ and D- lines.

4-layers isn't that much more expensive; Advanced Circuits has a 66 each deal for 4 layer boards that I use quite often for projects that use that very chip, as opposed to the 33 each deal for 2 layers.

In regards to your actual question...use plenty of bypass caps, as close to the pins as possible. If you split the bottom layer to have VCC and GND, don't have a trace cross the split on the top layer. Keep all high-speed signals on the top layer because the via inductance can kill what fragile signal integrity a 2-layer board has.

1) Crystals should not be routed this way. Traces should be shorter and as symmetrical as possible. You should connect capacitors to GND in a single point, so that you are not picking any noise from the ground plate. This is especially important for RTC crystal. With current routing you might get problems with generation start/failure if you are unlucky.

2) Checkout my single-layer board for ARM : http://hackaday.com/2011/08/03/an-arm-dev-board-you-can-make-at-home/ - even this nightmare works (only 1 decoupling cap). Defenitely what you have here will work. You may add some extra caps (like some 25uF electrolytic + 2.2uF ceramic) on the backside of the board, you have plenty of space there, and both VCC & GND together. The only thing I don't like is thin traces to your caps. They should be as wide as possible. In my design, the only capacitor was connected by like 2mm-wide traces.

Also, look at C5: You can move it to the right a little, move via closer to the cap and connect it with short wide track. When you via is under the chip, you cannot have wide tracks. Same for C6 and C7.

Also, if you are going to manufacture this at home,you'll have problems making vias under QFP chips.

3) Ground plate is more than enough. There is no much need to have solid ground plane except a square under chip where all decoupling caps are connected, it won't help with ground noise much. Ground plate is needed for controlled impedance, which is not important in your case. But your GND connection to contacts should be as wide as possible. This is general rule: VCC & GND nets should have wide tracks.

4) Yes, this is perfectly ok for low-speed ARMs.

In my case I even had no back side, and it was still working ;-) The only thing to improve if you are manufacturing on a factory is to have a small VCC square on the bottom layer in the middle of the chip, and connect it to the top using some 4-9 vias instead of 1. For VCC & GND planes you always need to have as low as possible resistances and inductance so that caps can easier filter noise => you need wider and shorter tracks and more parallel vias. But in this specific design it is not a requirement.

So, it will work even now without modifications. After mentioned changes it will be perfect.