Electronic – Minimizing(optimizing) digital logic circuit with multiplexer(s)

boolean-algebradigital-logiclogic-gatesmultiplexeroptimization

(this by the way was an exam question)

For \$F = \sum m(2, 3, 5, 7, 11, 13)\$, I am trying to implement a digital logic circuit using only the following:

  • 2:1 MUX (cost: 12, and must use at least one 2:1 MUX)
  • 2-input AND gate (cost: 6)
  • 2-input OR gate (cost: 6)
  • Inverter (cost: 2)

It obviously is pretty easy to implement it without any restrictions — that is, if I don't care about the cost at all. But if I were to minimize the cost, how should I go about it?

I first simplified \$F\$ using the K-map of it, and I got two representations of \$F\$, \$A\$ being the MSB:

  • \$F = BC'D + A'B'C + B'CD + A'CD\$
  • \$F = BC'D + A'B'C + B'CD + A'BD\$.

The second representation just looked nice to me because I can group all the product terms by \$B\$ like this:
\$F = BD(A'+C') + B'C(A'+D)\$. And apparently my design is indeed the implementation with the least cost — I got:My Design

But the way I solved it cannot be used for other expressions in general, and I honestly think I just got lucky. Is there a better way to solve this problem, that is, a general way that guarantees (or at least checks) that the implementation is that of minimal cost?

Best Answer

schematic

simulate this circuit – Schematic created using CircuitLab

$34 is the best I can do. Anyone else?

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