Electronic – Minimoog VCO analysis

There is no VCO 'reason' to have two varactors, they are functionally in parallel.

We therefore need to guess why the system found it convenient to provide two varactors.

The labelling of the tune lines to the varactors gives us a clue. \$V_T\$ is probably a 'tune' line, used to set the varactor to a coarse setting, static, as there is no t parameter. \$e_v(t)\$ is probably an error voltage back from the PLL, varying in time.

The relative weight of these two varactors can be set by the values of \$C_{D1}\$ and \$C_{D2}\$. A value larger than the varactor capacitance allows more or less the full varactor variation to affect the loop. A value much small than the varactor value attenuates the effective varactor swing at the PLL.

Why make \$C_T\$ a manually adjusted variable? It might be for a coarse pre-setting of the centre frequency of the VCO. However that type of VCO needs a particular range of capacitor ratios to actually oscillate. Perhaps the FET used has large enough parasitic variations that each one needs to be tuned after manufacture.

Noise in a VCO is a parameter that's particularly difficult to guess at from just a circuit diagram. There's a wide range of applications for PLLs, some of which require exquisitely low noise, others of which don't. That might have driven the separation of the varactors, rather than use a single varactor with a composite drive, and a manual adjuster control to 'peak up' the VCO, who knows?

This is called a differential amplifier

^{simulate this circuit – Schematic created using CircuitLab}

A constant current source draws a constant combined current through the emitters of transistors Q1 and Q2.

If the voltage at V_in1 is equal to the reference voltage REF, and assuming that the transistors are identical, then the currents through Q1 and Q2 are the same, and hence the currents into I_out1+ and I_out1- are also the same.

Lets say we start increasing the base current of Q1 (by applying an input signal) then the emitter current of Q1 is going to increase and since the combined emitter currents from Q1 and Q2 must be constant so must the emitter current of Q2 decrease an equal amount. This causes an increase of current into I_out1+ and a decrease of current into I_out1-.

Now since the current through the base of Q1 is logarithmically related to the voltage across the base so if we let the voltage on V_in1 increase then the base current is going to increase logarithmically.

This circuit produces a constant current proportional to V_in2

^{simulate this circuit}

Any voltage at V_in2 greater then 0v is going to cause a current to flow through R1 and out of I_out2-. If this causes any increase in voltage at the inverting input of the opamp then it is going to decrease the voltage on the output in an attempt to keep the voltage at the inverting input at 0v. This causes a constant current to flow between I_out2- and I_out2+.

Now lets combine them

^{simulate this circuit}

Does it start to look familiar?

The current at I_out1- is proportional to the voltage at V_in2 and log proportional to the voltage at V_in1.